Voltage mode weak-PUF circuit with rich challenge-response pairs

Patent metadata

Field	Value
Publication number	US-12417321-B2
Application number	US-202418418350-A
Country	US
Kind code	B2
Filing date	Jan 22, 2024
Priority date	Nov 7, 2023
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A voltage mode weak-PUF circuit with rich challenge-response pairs comprises four decoders, two PUF arrays, a sequential control circuit and a voltage comparator. One-to-two PUF arrays are used to replace existing one-to-one PUF arrays to increase the number of challenge-response pairs by 2N times, from 2N realized by the one-to-one PUF arrays to 2N×2N, wherein N=a+b. Each PUF cell comprises m*n PUF cells and n transmission gates, and adopts a simple common-source amplifier structure formed by a first PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein any one PUF cell in one PUF array can be compared with any one PUF cell in the other PUF array to generate an output response. The number of output responses is 2N, so the proportion of the PUF cells for generating one challenge-response pair is 2N/2N=1/2N, and the reuse rate of the same PUF cell is merely 1/2N.

First claim

What is claimed is:

1. A voltage mode weak-PUF (physically unclonable function) circuit with rich challenge-response pairs, comprising four decoders, two PUF arrays, a sequential control circuit and a voltage comparator, wherein each PUF array comprises m*n PUF cells and n transmission gates, m=2 a , a is an integer greater than or equal to 1, n=2 b , b is an integer greater than or equal to 1, the m*n PUF cells are distributed in m rows and n columns, the n transmission gates are distributed in one row and n columns, each transmission gate has a control terminal, an input terminal and an output terminal, each PUF cell has a first input terminal, a second input terminal and an output terminal, and comprises a first P-type metal-oxide-semiconductor (PMOS) transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor and a second NMOS transistor, a supply voltage (VDD) is accessed to a source of the first PMOS transistor, a gate of the first PMOS transistor, a drain of the first PMOS transistor and a drain of the second NMOS transistor are connected and a connecting terminal thereof is the output terminal of the PUF cell, a gate of the second NMOS transistor is the second input terminal of the PUF cell, a source of the second NMOS transistor and a drain of the first NMOS transistor are connected, a gate of the first NMOS transistor is the first input terminal of the PUF cell, and a source of the first NMOS transistor is grounded; in each PUF array, the first input terminals of the n PUF cells in the j th row are connected and a connecting terminal thereof is a j th row address input terminal of the PUF array, j=1, 2, . . . , m, a first row address input terminal to an m th row address input terminal of the PUF array form an m-bit row address input terminal of the PUF array, the second input terminals of the m*n PUF cells are connected and a connecting terminal thereof is a sub-threshold input terminal of the PUF array, to which a sub-threshold voltage (VBB) is accessed, the control terminal of the k th transmission gate is a k th column address input terminal of the PUF array, k=1, 2, . . . , n, a first column address input terminal to an n th column address input terminal of the PUF array form an n-bit column address input terminal of the PUF array, and the input terminal of the k th transmission gate is connected to the output terminals of the m PUF cells in the k th column; the output terminals of the n transmission gates are connected and a connecting terminal thereof is an output terminal of the PUF array; the two PUF arrays are referred to as a first PUF array and a second PUF array respectively; the sequential control circuit is configured to provide an enable control signal for the four decoders and the voltage comparator to enable the four decoders, the two PUF arrays and the voltage comparator to operate cooperatively in a preset sequence; the four decoders are referred to a first decoder, a second decoder, a third decoder and a fourth decoder respectively; a first row selection signal is accessed to the first decoder and is converted by the first decoder into a first m-bit row address signal, which is output to the m-bit row address input terminal of the first PUF array, a first column selection signal is accessed to the second decoder and is converted by the second decoder into a first n-bit column address signal, which is output to the n-bit column address input terminal of the first PUF array, the first m-bit row address signal is used for selecting n PUF cells in one row of the first PUF array to enable the n PUF cells in said row to enter an operating state to generate output signals, the first n-bit column address signal is used for selecting one PUF cells from the n selected PUF cells in the first PUF array and outputting an output signal generated by the selected PUF cell to the voltage comparator, as an output signal of the first PUF array, a second row selection signal is accessed to the third decoder and is converted by the third decoder into a second m-bit row address signal, which is output to the m-bit row address input terminal of the second PUF array, a second column selection signal is accessed to the fourth decoder and is converted by the fourth decoder into a second n-bit column address signal, which is output to the n-bit column address input terminal of the second PUF array, the second m-bit row address signal is used for selecting n PUF cells in one row of the second PUF array to enable the n PUF cells in said row to enter an operating state to generate output signals, the second n-bit column address signal is used for selecting one PUF cell from the n selected PUF cells in said row of the second PUF array and outputting an output signal generated by the selected PUF cell to the voltage comparator, as an output signal of the second PUF array, and the voltage comparator is configured to compare the two output signals output thereto by the first PUF array and the second PUF array to obtain and output a response signal.

2. The voltage mode weak-PUF circuit with rich challenge-response pairs according to claim 1 , wherein m is equal to 64, n is equal to 8, the first decoder and the second decoder are both 6-bit decoders and are able to convert 6-bit binary data output thereto into 64-bit binary data and output the 64-bit binary data, the second decoder and the fourth decoder are both 3-bit decoders and are able to convert 3-bit binary data output thereto into 8-bit binary data and output the 8-bit binary data, the first row selection signal and the second row selection signal are both 6-bit binary data, and the first column selection signal and the second column selection signal are both 3-bit binary data; the sequential control circuit generates a first enable control signal (EN_L) and a second enable control signal (EN_C), wherein the first enable control signal (EN_L) is output to the first decoder, the second decoder, the third decoder and the fourth decoder respectively, and the second enable control signal (EN_C) is output to the voltage comparator; when the first enable control signal (EN_L) is a high level, the first decoder and the third decoder operate to perform decoding, and the second decoder and the fourth decoder do not operate and hold the current state; when the first enable controls signal (EN_L) is a low level, the first decoder and the third decoder do not operate and hold the current state, and the second decoder and the fourth decoder operate to perform decoding; when the second enable control signal (EN_C) is a high level, the voltage comparator operates to compare the output signals output thereto by the two PUF arrays to obtain and output the response signal; and when the second enable control signal (EN_C) is a low level, the voltage comparator is turned off, and no valid value is output via an output terminal of the voltage comparator.

3. The voltage mode weak-PUF circuit with rich challenge-response pairs according to claim 2 , wherein the voltage comparator has a first input terminal, a second input terminal, an enable terminal, a first calibration terminal, a second calibration terminal and an output terminal, wherein the first input terminal of the voltage comparator is connected to the output terminal of the first PUF array, the second input terminal of the voltage comparator is connected to the output terminal of the second PUF array, the enable terminal of the voltage comparator is connected to the sequential control circuit and allows the second enable control signal (EN_C) to be accessed thereto, a first calibration voltage (Vcm) is accessed to the first calibration terminal of the voltage comparator, a second calibration voltage (Vcp) is accessed to the second calibration terminal of the voltage comparator, and the first calibration voltage (Vcm) and the second calibration voltage (Vcp) are used for enabling the p

Assignees

• Univ Wenzhou

Inventors

• Li Gang
• Wang Pengjun
• Li Hui
• Zhou Ziyu

Classifications

• G06F2221/2103

  Challenge-response · CPC title

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• H03K19/094

  using field-effect transistors · CPC title

• G06F21/75 Primary

  by inhibiting the analysis of circuitry or operation · CPC title