Integrated circuit that mitigates inductive-induced voltage droop using compute unit group identifiers

Patent metadata

Field	Value
Publication number	US-12416961-B2
Application number	US-202318132392-A
Country	US
Kind code	B2
Filing date	Apr 8, 2023
Priority date	Sep 9, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

An integrated circuit (IC) includes an array of statically reconfigurable compute units for separation into mutually exclusive groups. Each group includes statically reconfigurable number of compute units. Each compute unit includes a register statically reconfigurable with a group identifier that identifies which group the compute unit belongs to, a counter statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle, and control circuitry that prevents the compute unit from starting to process data until the counter value matches the identifier. According to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

First claim

The invention claimed is:

1. An integrated circuit (IC), comprising:
an array of compute units that are statically reconfigurable for separation into mutually exclusive groups, wherein each group includes no more than a statically reconfigurable number of compute units, wherein each compute unit comprises:
a register statically reconfigurable with a group identifier that identifies which group of the mutually exclusive groups the compute unit belongs to;
a counter, statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle; and
control circuitry that prevents the compute unit from starting to process data until the counter value matches the group identifier;
wherein according to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

2. The IC of claim 1 ,
wherein each compute unit further comprises:
a second counter that increments each clock cycle and resets to zero upon reaching a statically reconfigurable maximum value;
wherein the first counter is incremented by the second counter reaching the statically reconfigurable maximum value; and
wherein the statically reconfigurable maximum value specifies a minimum delay in clock cycles between which each group of compute units starts to process data.

3. The IC of claim 2 ,
wherein each compute unit is configured to receive an execute command from a master unit after the IC is statically reconfigured;
wherein each compute unit receives the execute command a variable number of clock cycles after transmission of the execute command by the master unit, and the number of clock cycles varies due to a location of the compute unit within the array relative to the master unit; and
wherein the second counter is statically reconfigured with an initial value based on the number of clock cycles associated with the unit so that all the first counters have the same value each clock cycle.

4. The IC of claim 3 ,
wherein the first counter is statically reconfigured with an initial value based on the number of clock cycles associated with the unit so that all the first counters have the same value each clock cycle after all the second counters have reached the statically reconfigurable maximum value at least once.

5. The IC of claim 1 ,
wherein the counter resets to zero after incrementing to a statically reconfigurable group identifier value that corresponds to a last of the mutually exclusive groups.

6. The IC of claim 1 ,
wherein the control circuitry comprises a state machine having inactive, wait, and run states;
wherein the state machine transitions from the inactive state to the wait state in response to an indication that all data dependencies of the compute unit are satisfied;
wherein the state machine transitions from the wait state to the run state in response to the match of the counter value and the group identifier; and
wherein control circuitry prevents the compute unit from starting to process data until the state machine enters the run state.

7. The IC of claim 6 ,
wherein each compute unit further comprises:
a second counter that increments each clock cycle in which the compute unit is not processing data;
wherein the state machine transitions from the run state to the inactive state in response to the second counter reaching a statically reconfigurable maximum value.

8. The IC of claim 7 ,
wherein the second counter is reset by a transition from the wait state to the run state; and
wherein the second counter is reset by the compute unit processing data.

9. An integrated circuit (IC), comprising:
an array of compute units that are statically reconfigurable for separation into mutually exclusive groups, wherein each compute unit comprises:
a register statically reconfigurable with a group identifier that identifies which group of the mutually exclusive groups the compute unit belongs to;
a first counter that increments each clock cycle and resets to zero when reaching a statically reconfigurable delay value;
a second counter that increments each time the first counter reaches the delay value; and
control circuitry that prevents the compute unit from starting to process data until the second counter value matches the group identifier;
wherein according to operation of the register, the first counter, the second counter, and the control circuitry, only one group of the mutually exclusive groups of compute units is allowed to start processing data concurrently within each window of the delay value clock cycles to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

10. The IC of claim 9 ,
wherein each group includes no more than a statically reconfigurable number of compute units.

11. The IC of claim 9 ,
wherein the second counter resets to zero when reaching a statically reconfigurable maximum group identifier value.

12. The IC of claim 9 ,
wherein each compute unit further comprises:
a third counter that increments each clock cycle in which the compute unit is not processing data;
wherein when the third counter reaches a statically reconfigurable maximum value, the control circuitry prevents the compute unit from starting to process data until the second counter value matches the group identifier again.

13. A method, comprising:
in an integrated circuit (IC) comprising an array of compute units that are statically reconfigurable for separation into mutually exclusive groups, wherein each group includes no more than a statically reconfigurable number of compute units, wherein each compute unit comprises a register, a counter, and control circuitry:
statically reconfiguring the register with a group identifier that identifies which group of the mutually exclusive groups the compute unit belongs to;
statically reconfiguring the counter to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle;
preventing, by the control circuitry, the compute unit from starting to process data until the counter value matches the group identifier; and
wherein according to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

14. The method of claim 13 ,
wherein each compute unit further comprises:
a second counter that increments each clock cycle and resets to zero upon reaching a statically reconfigurable maximum value;
wherein the first counter is incremented by the second counter reaching the statically reconfigurable maximum value; and
wherein the statically reconfigurable maximum value specifies a minimum delay in clock cycles between which each group of compute units starts to process data.

15. The method of claim 14 , further comprising:
receiving, by each compute unit, an execute command from a master unit after the IC is statically reconfigured;
wherein each compute unit receives the execute command a variable number of clock cycles after transmission of the execute command by the master unit, and the number of clock cycles varies due to a locatio

Assignees

• Sambanova Systems Inc

Inventors

• Gandhi Darshan
• Shah Manish K
• Prabhakar Raghu
• Grohoski Gregory Frederick
• Choi Youngmoon
• Shin Jinuk

Classifications

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03K19/17784

  for supply voltage · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title