Apparatus, systems, and methods for intelligent tuning of overclocking frequency

Patent metadata

Field	Value
Publication number	US-12416938-B2
Application number	US-202117558118-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Apparatus, systems, and methods for intelligent tuning of overclocking frequency are disclosed. An example apparatus includes trial control circuitry to execute an optimization model to select first values for overclocking parameters of a processor, the first values associated with a first trial, and perform benchmark testing of the processor when the processor is operating based on the first values; trial evaluation circuitry to calculate a first score for the first trial based on the benchmark testing; and model updating circuitry to perform a comparison of the first score to a second score, the second score associated with a second trial for second values for the overclocking parameters, the second values different than the first values; and select one of the first values or the second values to overclock the processor based on the comparison.

First claim

What is claimed is:

1. An apparatus comprising:
machine-readable instructions; and
at least one programmable circuit to instantiate:
trial control circuitry to:
execute an optimization model to select first values for overclocking parameters of one or more of the at least one programmable circuit, the first values associated with a first trial; and
perform benchmark testing of the one or more of the at least one programmable circuit when the one or more of the at least one programmable circuit is operating based on the first values;

trial evaluation circuitry to:
assign benchmark scores to respective tests of the benchmark testing of the first trial;
identify at least one of the tests as associated with a crash event;
responsive to the crash event, apply a penalty to one or more of the benchmark scores corresponding to a test not associated with the crash event to calculate a first score for the first trial based on the benchmark testing; and

model updating circuitry to:
perform a comparison of the first score to a second score, the second score associated with a second trial for second values for the overclocking parameters, the second values different than the first values; and
select one of the first values or the second values to overclock the one or more of the at least one programmable circuit based on the comparison.

2. The apparatus of claim 1 , wherein the model updating circuitry is to update the optimization model based on the first score to generate an updated optimization model.

3. The apparatus of claim 2 , wherein the trial control circuitry is to execute the updated optimization model to select third values for the overclocking parameters.

4. The apparatus of claim 1 , wherein one or more of the at least one programmable circuit is to instantiate cooler monitoring circuitry to:
determine a temperature of the one or more of the at least one programmable circuit prior to the benchmark testing based on data from a cooler; and
instruct the cooler to increase cooling of the one or more of the at least one programmable circuit to reduce the temperature of the one or more of the at least one programmable circuit prior to the benchmark testing.

5. The apparatus of claim 1 , wherein the overclocking parameters includes a first overclocking parameter, the first values include a first value for the first overclocking parameter, and one or more of the at least one programmable circuit is to instantiate component interface circuitry to obtain a minimum value for the first overclocking parameter and a maximum value for the first overclocking parameter, the trial control circuitry to execute the optimization model to select the first value for the first overclocking parameter based on the minimum value and the maximum value.

6. The apparatus of claim 5 , wherein the first overclocking parameter includes one of a core voltage, a core ratio, or a temperature threshold.

7. The apparatus of claim 1 , wherein the at least one of the tests associated with the crash event includes a first test and the trial evaluation circuitry is to:
identify a second test as associated with a performance event at a cooler; and
apply the penalty to one or more of the benchmark scores corresponding to a test not associated with the crash event and not associated with the performance event at the cooler.

8. An apparatus comprising:
at least one memory;
machine-readable instructions; and
at least one processor circuit to be programmed by the machine-readable instructions to:
select a first set of overclocking parameter values and a second set of overclocking parameter values, the first set of overclocking parameter values different than the second set of overclocking parameter values;
perform first benchmark testing based on the first set of overclocking parameter values;
perform second benchmark testing based on the second set of overclocking parameter values;
associate respective benchmark runs of the first benchmark testing with corresponding first benchmark scores;
calculate a first score for the first set of overclocking parameter values based on the first benchmark scores and a penalty factor, the penalty factor associated with a processor crash event;
associate respective benchmark runs of the second benchmark testing with corresponding second benchmark scores;
calculate a second score for the second set of overclocking parameter values based on the second benchmark scores; and
select one of the first set of overclocking parameter values or the second set of overclocking parameter values to be used to increase a processor clock rate based on the first score and the second score.

9. The apparatus of claim 8 , wherein one or more of the at least one processor circuit is to execute an optimization model to select the first set of overclocking parameter values.

10. The apparatus of claim 9 , wherein one or more of the at least one processor circuit is to update the optimization model based on the first set of overclocking parameter values.

11. The apparatus of claim 8 , wherein one or more of the at least one processor circuit is to select the first set of overclocking parameter values based on respective ranges defining minimum and maximum values for the overclocking parameter values.

12. The apparatus of claim 8 , wherein one or more of the at least one processor circuit is to calculate the first second score based on an average of the second benchmark scores.

13. The apparatus of claim 8 , wherein one or more of the at least one processor circuit is to detect an operational status of a cooler prior to the performance of the first benchmark testing.

14. A non-transitory computer readable storage medium comprising machine-readable instructions to cause at least one processor circuit to at least:
execute a model to predict a first overclocking parameter value for one or more of the at least one processor circuit;
perform first benchmark testing of the one or more of the at least one processor circuit operated based on the first overclocking parameter value, the performance of the first benchmark testing including a plurality of repeated benchmark tests associated with operation based on the first overclocking parameter value;
assign benchmark scores to respective ones of the repeated benchmark tests;
generate a penalized benchmarking score by applying a penalty based on a performance event to one or more of the benchmark scores corresponding to a benchmark test not associated with the performance event;
initiate re-training of the model based on the first overclocking parameter value and the penalized benchmarking score to generate an updated model;
execute the updated model to predict a second overclocking parameter value, the first overclocking parameter value different than the second overclocking parameter value;
perform second benchmark testing based on the second overclocking parameter value;
associate the second overclocking parameter value with a second score based on the second benchmark testing; and
select one of the first overclocking parameter value or the second overclocking parameter value to cause overclocking based on the first penalized benchmarking score and the second score.

15. The non-transitory computer readable storage medium of claim 14 , wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to train the updated model based on the second overclocking parameter value and the second score.

16. The non-transitory computer readable storage medium of claim 14 , wherein the machine-readable instructio

Assignees

• Intel Corp

Inventors

• Yan Jin
• Xiong Hui
• Zhu Jianfang
• Gonzalez Felipe
• Macdonald Mark
• Ragland Daniel
• Rodriguez Rodny
• Fife Matthew
• Li Yifan
• Fleming Kristoffer

Classifications

• G06F1/206 Primary

  comprising thermal management · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title