Display panel

Patent metadata

Field	Value
Publication number	US-12416839-B2
Application number	US-202318297016-A
Country	US
Kind code	B2
Filing date	Apr 7, 2023
Priority date	May 18, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A display panel includes a substrate, pixels, gate lines, a gate connecting line, a common line and a compensation electrode. The pixels are disposed on the substrate. The gate lines are disposed on the substrate and are configured to receive scan signals. The number of pixels coupled to a first gate line of the gate lines is less that the number of pixels coupled to a second gate line of the gate lines. The gate connecting line is electrically connected to the first gate line. The common line is disposed under the gate connecting line, and is configured to receive a common voltage signal. The compensation electrode is disposed over the gate connecting line, and is configured to receive the common voltage signal. The common line, the gate connecting line and the compensation electrode are overlapped.

First claim

What is claimed is:

1. A display panel having an active area and a peripheral area and comprising:
a substrate;
a plurality of pixels disposed on the substrate and in the active area;
a plurality of gate lines disposed on the substrate and configured to receive a plurality of scan signals, wherein each gate line is coupled to one or more of the pixels, wherein a number of pixels coupled to a first gate line of the gate lines is less than a number of pixels coupled to a second gate line of the gate lines, and wherein the first gate line crosses the active area and the peripheral area;
a gate connecting line in the peripheral area and electrically connected to the first gate line;
a common line in the peripheral area and disposed under the gate connecting line, the common line configured to receive a common voltage signal; and
a compensation electrode in the peripheral area and disposed over the gate connecting line, the compensation electrode configured to receive the common voltage signal;
wherein the common line, the gate connecting line and the compensation electrode are overlapped in a normal direction of the display panel.

2. The display panel of claim 1 , further comprising:
a bridge structure in the peripheral area and directly connecting the first gate line and the gate connecting line.

3. The display panel of claim 2 , wherein each pixel comprises a pixel electrode and a common electrode, wherein the common electrode is disposed over the pixel electrode, and wherein the common electrode, the bridge structure and the compensation electrode belong to the same transparent conductive layer.

4. The display panel of claim 2 , further comprising:
a compensation wiring in the peripheral area and disposed over the compensation electrode, the compensation wiring configured to receive the same scan signal as the first gate line;
wherein the common line, the gate connecting line, the compensation electrode and the compensation wiring are overlapped in the normal direction of the display panel.

5. The display panel of claim 4 , wherein the compensation wiring directly connects the bridge structure and the gate connecting line.

6. The display panel of claim 1 , wherein each pixel comprises a pixel electrode and a common electrode, wherein the common electrode is disposed under the pixel electrode, and wherein the common electrode and the compensation electrode belong to the same transparent conductive layer.

7. The display panel of claim 1 , wherein a width of the common line is greater than a width of the gate connecting line.

8. The display panel of claim 1 , wherein the active area is free-shaped and has a first subarea and a second subarea, wherein the first subarea and the second subarea are opposite to each other and have a gap therebetween, and wherein the common line and the gate connecting line are disposed in the gap.

9. A display panel having an active area and a peripheral area and comprising:
a substrate;
a plurality of pixels disposed on the substrate and in the active area;
a plurality of gate lines disposed on the substrate and configured to receive a plurality of scan signals, wherein each gate line is coupled to one or more of the pixels, wherein a number of pixels coupled to a first gate line of the gate lines is less than a number of pixels coupled to a second gate line of the gate lines, and wherein the first gate line crosses the active area and the peripheral area;
a common line disposed over the first gate line and in the peripheral area, the common line configured to receive a common voltage signal;
a compensation wiring disposed over the common line, the compensation wiring configured to receive the same scan signal as the first gate line; and
a compensation electrode disposed over the compensation wiring, the compensation electrode configured to receive the common voltage signal;
wherein the first gate line, the common line, the compensation wiring and the compensation electrode are overlapped in a normal direction of the display panel.

10. The display panel of claim 9 , further comprising:
a bridge structure in the peripheral area and directly connecting the first gate line and the compensation wiring.

11. The display panel of claim 10 , wherein each pixel comprises a pixel electrode and a common electrode, wherein the common electrode is disposed under the pixel electrode, and wherein the pixel electrode, the bridge structure and the compensation electrode belong to the same transparent conductive layer.

Assignees

• Hannstar Display Corp

Inventors

• Kang Mu-Kai
• Yeh Cheng-Yen
• Huang Sz-Kai
• Chen Jing-Xuan
• Chen Yen-Chung

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H04M1/0266

  for a display module assembly · CPC title

• G02F1/13452

  Conductors connecting driver circuitry and terminals of panels · CPC title

• G02F2201/121

  common or background · CPC title