Printed circuit board, fabrication method of the same and electronic device including the same

Patent metadata

Field	Value
Publication number	US-12414230-B2
Application number	US-202217968308-A
Country	US
Kind code	B2
Filing date	Oct 18, 2022
Priority date	Oct 15, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A printed circuit board and/or an electronic device including the same are provided. The printed circuit board and/or an electronic device includes at least one insulation layer including a first rigid region and a flexible region extending from the first rigid region, at least one first circuit pattern disposed on one surface of the at least one insulation layer to at least partially transverse the flexible region from the first rigid region, and at least one conductive pad formed at least partially on a surface of the first circuit pattern in the first rigid region, wherein the flexible region may be configured to flexibly deform more than the first rigid region.

First claim

What is claimed is:

1. A printed circuit board comprising:
at least one insulation layer comprising a first rigid region and a flexible region extending from the first rigid region;
at least one first circuit pattern disposed on a first surface of the at least one insulation layer to at least partially transverse the flexible region from the first rigid region; and
at least one conductive pad at least partially disposed on a surface of the at least one first circuit pattern in the first rigid region,
wherein a sum of thicknesses of the at least one conductive pad and the at least one first circuit pattern from the first surface of the at least one insulation layer in the first rigid region is 1.5 times to 4.0 times the thickness of the at least one first circuit pattern in the flexible region,
wherein the at least one conductive pad comprises a plating layer at least partially grown on the surface of the at least one first circuit pattern,
wherein the flexible region is configured to flexibly deform more than the first rigid region,
wherein at least a portion of the at least one first circuit pattern comprises at least a portion of an electrically conductive film laminated on the first surface of the at least one insulation layer, and
wherein the electrically conductive film includes a rolled copper foil and has higher durability regard to repeated deformation than a durability of the plating layer or an electrolytic copper foil.

2. The printed circuit board of claim 1 , a side surface of the at least one conductive pad is formed to be at least partially inclined with respect to the first surface of the at least one insulation layer or the surface of the at least one first circuit pattern.

3. The printed circuit board of claim 1 ,
wherein the at least one insulation layer further comprises a second rigid region connected to the first rigid region through the flexible region, and
wherein the flexible region is configured to flexibly deform more than the second rigid region.

4. The printed circuit board of claim 3 , wherein the at least one first circuit pattern further comprises another portion disposed in the second rigid region.

5. The printed circuit board of claim 1 , further comprising:
at least one via conductor disposed to pass through the at least one insulation layer in the first rigid region,
wherein the at least one via conductor comprises at least a portion of a plating layer integrally formed with the at least one conductive pad.

6. The printed circuit board of claim 1 , further comprising:
a second circuit pattern disposed on a second surface of the at least one insulation layer so as to extend from the first rigid region and to at least partially transverse the second surface of the flexible region; and
at least one via conductor disposed to pass through the at least one insulation layer in the first rigid region,
wherein the at least one via conductor is configured to electrically connect the second circuit pattern to the at least one first circuit pattern.

7. The printed circuit board of claim 6 , further comprising:
at least one via hole disposed to pass through the at least one insulation layer,
wherein the at least one via conductor comprises a plating layer disposed on the at least one via hole while being in contact with the second circuit pattern, and
wherein the at least one conductive pad comprises a plating layer disposed in contact with the at least one first circuit pattern while being connected to the at least one via conductor.

8. The printed circuit board of claim 1 ,
wherein a plurality of insulation layers are sequentially stacked,
wherein the at least one first circuit patterns comprises a plurality of the first circuit patterns, and
wherein the plurality of the first circuit patterns are disposed between two adjacent insulation layers among the plurality of insulation layers or on at least a portion of the first surface of an outermost insulation layer among the plurality of insulation layers, respectively.

9. The printed circuit board of claim 8 , comprising:
at least one via hole disposed to pass through at least one insulation layer of the plurality of insulation layers; and
a via conductor comprising a plating layer disposed on the at least one via hole,
wherein the via conductor is configured to electrically connect two adjacent first circuit patterns positioned on different layers among the plurality of the first circuit patterns.

10. The printed circuit board of claim 9 , wherein the at least one conductive pad is a plating layer connected to the via conductor and is disposed in contact with one of the plurality of the first circuit patterns.

11. An electronic device comprising:
a first housing;
a second housing coupled to the first housing and coupled to be rotatable with respect to the first housing;
a hinge structure configured to rotatably couple the second housing to the first housing; and
a printed circuit board according to claim 1 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ha Sangwon
• Yang Hyunmo
• Chung Yeonkyung
• Chi Younoh

Classifications

• H05K3/421

  Blind plated via connections (H05K3/422, H05K3/423 and H05K3/425 take precedence) · CPC title

• H05K2203/143

  Treating holes before another process, e.g. coating holes before coating the substrate · CPC title

• H05K2201/09545

  Plated through-holes or blind vias without lands · CPC title

• H05K2201/09481

  Via in pad; Pad over filled via · CPC title

• H05K2203/1461

  Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors · CPC title