Method for transmitting and receiving signals in wireless communication system, and device supporting same

Patent metadata

Field	Value
Publication number	US-12414061-B2
Application number	US-202418402304-A
Country	US
Kind code	B2
Filing date	Jan 2, 2024
Priority date	Nov 2, 2018
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

The present invention relates to a wireless communication system, and in particular, to a method and a device therefor, in which a sequence for a primary sidelink synchronization signal (PSSS) is generated on the basis of a specific cyclic shift value, and the PSSS is transmitted to a second device on the basis of the generated sequence, wherein the specific cyclic shift value is one of a plurality of first cyclic shift values for the PSSS, the plurality of first cyclic shift values are on the basis of a certain ratio being applied to offsets of second cyclic shift values for a downlink primary synchronization signal (DL PSS) sequence, and the intervals between the plurality of first cyclic shift values are maximized.

First claim

What is claimed is:

1. A method performed by a device, the method comprising:
generating a Primary Sidelink Synchronization Signal (PSSS) based on a first cyclic shift (CS) value; and
generating a Secondary Sidelink Synchronization Signal (SSSS) based on a first binary sequence and a second binary sequence; and
transmitting the PSSS and the SSSS,
wherein the first CS value is determined based on whether the device is in-coverage or out-of-coverage, and
wherein the first CS value is determined based on a first set of CS values different from a second set of CS values for a Primary Synchronization Signal (PSS).

2. The method of claim 1 , wherein a CS value in the first set is related to a ceiling function or a floor function to a half of a CS value in the second set.

3. The method of claim 1 , wherein the first binary sequence is related to a plurality of CS values having a first interval, and
wherein the second binary sequence is related to a plurality of CS values having a second interval being different form the first interval.

4. The method of claim 3 , wherein the first interval is 5, and the second interval is 1.

5. The method of claim 1 , wherein a first polynomial is used for the PSSS and two second polynomials are used for the SSSS.

6. The method of claim 5 , wherein one of the two second polynomials is identical to the first polynomial.

7. The method of claim 6 , wherein initial values for the one of the two second polynomials are different from initial values for the first polynomial.

8. The method of claim 1 , wherein the device is a user equipment (UE).

9. The method of claim 1 , wherein the first binary sequence is a first M-sequence, and the second binary sequence is a second M-sequence.

10. The method of claim 1 , wherein the first set includes {22, 65}, and the second set includes {0, 43, 86}.

11. A device comprising:
at least one processor; and
at least one computer memory operably connectable to the at least one processor and storing instructions that, when executed by the at least one processor, perform operations comprising:
generating a Primary Sidelink Synchronization Signal (PSSS) based on a first cyclic shift (CS) value; and
generating a Secondary Sidelink Synchronization Signal (SSSS) based on a first binary sequence and a second binary sequence; and
transmitting the PSSS and the SSSS,
wherein the first CS value is determined based on whether the device is in-coverage or out-of-coverage, and
wherein the first CS value is determined based on a first set of CS values different from a second set of CS values for a Primary Synchronization Signal (PSS).

12. The device of claim 11 , further comprising:
at least one transceiver,
wherein the device is a user equipment (UE).

13. The device of claim 11 , wherein the device is a processing device configured to control a user equipment (UE) in a wireless communication system.

14. The device of claim 11 , wherein a CS value in the first set is related to a ceiling function or a floor function to a half of a CS value in the second set.

15. The device of claim 11 , wherein the first binary sequence is related to a plurality of CS values having a first interval, and
wherein the second binary sequence is related to a plurality of CS values having a second interval being different form the first interval.

16. The device of claim 15 , wherein the first interval is 5, and the second interval is 1.

17. The device of claim 11 , wherein a first polynomial is used for the PSSS and two second polynomials are used for the SSSS.

18. The device of claim 17 , wherein one of the two second polynomials is identical to the first polynomial.

19. The device of claim 18 , wherein initial values for the one of the two second polynomials are different from initial values for the first polynomial.

20. A non-transitory medium storing instructions, when executed by at least one processor, that cause at least one processor to perform operations, the operations comprising:
generating a Primary Sidelink Synchronization Signal (PSSS) based on a first cyclic shift (CS) value; and
generating a Secondary Sidelink Synchronization Signal (SSSS) based on a first binary sequence and a second binary sequence; and
transmitting the PSSS and the SSSS,
wherein the first CS value is determined based on whether the at least one processor is in-coverage or out-of-coverage, and
wherein the first CS value is determined based on a first set of CS values different from a second set of CS values for a Primary Synchronization Signal (PSS).

Assignees

• Lg Electronics Inc

Inventors

• Ko Hyunsoo
• Kim Youngsub
• Seo Hanbyul
• Yoon Sukhyon
• Chae Hyukjin

Classifications

• H04L27/2605

  Symbol extensions, e.g. Zero Tail, Unique Word [UW] · CPC title

• H04W4/40

  for vehicles, e.g. vehicle-to-pedestrians [V2P] · CPC title

• H04L27/2613

  Structure of the reference signals · CPC title

• H04W76/14

  Direct-mode setup · CPC title

• H04J13/00

  Code division multiplex systems (for frequency hopping H04B1/713) · CPC title