Image sensor and image processing system

Patent metadata

Field	Value
Publication number	US-12413872-B2
Application number	US-202318190975-A
Country	US
Kind code	B2
Filing date	Mar 28, 2023
Priority date	Sep 30, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

Disclosed is an image sensor including a first tap pixel, a second tap pixel, and an overflow detection circuit suitable for detecting overflow of the first tap pixel based on a first tap pixel signal outputted from the first tap pixel and overflow of the second tap pixel based on a second tap pixel signal outputted from the second tap pixel, and forming a current path from an overflow current source to a ground voltage terminal when a voltage of the first tap pixel signal or a voltage of the second tap pixel signal drops below a predetermined voltage.

First claim

What is claimed is:

1. An image sensor comprising:
a first tap pixel;
a second tap pixel; and
an overflow detection circuit suitable for:
detecting overflow of the first tap pixel based on a first tap pixel signal outputted from the first tap pixel and overflow of the second tap pixel based on a second tap pixel signal outputted from the second tap pixel, and
forming a current path from an overflow current source to a ground voltage terminal when a voltage of the first tap pixel signal or a voltage of the second tap pixel signal drops below a predetermined voltage.

2. The image sensor of claim 1 , wherein the overflow detection circuit is further suitable for outputting an overflow detection signal whose voltage is changed by the formed current path.

3. The image sensor of claim 2 , wherein when a voltage detected at a node, from which the first tap pixel signal or the second tap pixel signal is outputted, drops below the predetermined voltage, a first PMOS transistor coupled to an output node of the first tap pixel or a second PMOS transistor coupled to an output node of the second tap pixel is turned on and the current path is formed from the overflow current source to the ground voltage terminal so that a voltage of the overflow detection signal shifts from a logic high level to a logic low level.

4. The image sensor of claim 1 , wherein the first tap pixel includes:
a first photodetector connected to a first node;
a first reset transistor suitable for resetting the first node in response to a reset signal;
a first transfer transistor suitable for electrically connecting the first node to a first floating diffusion node in response to a transfer signal;
a first capacitor connected to the first floating diffusion node;
a first driving transistor suitable for amplifying a voltage of the first floating diffusion node; and
a first selection transistor suitable for outputting the voltage amplified by the first driving transistor to a first tap output line in response to a first selection signal.

5. The image sensor of claim 1 , wherein the second tap pixel includes:
a second photodetector connected to a second node;
a second reset transistor suitable for resetting the second node in response to a reset signal;
a second transfer transistor suitable for electrically connecting the second node to a second floating diffusion node in response to a transfer signal;
a second capacitor connected to the second floating diffusion node;
a second driving transistor suitable for amplifying a voltage of the second floating diffusion node; and
a second selection transistor suitable for outputting the voltage amplified by the second driving transistor to a second tap output line in response to a second selection signal.

6. An image processing system comprising:
a pixel array including a plurality of first tap pixels and a plurality of second tap pixels;
an overflow detection circuit suitable for detecting overflow of the plurality of first tap pixels based on a plurality of first tap pixel signals outputted from the plurality of first tap pixels and overflow of the plurality of second tap pixels based on a plurality of second tap pixel signals outputted from the plurality of second tap pixels; and
an image processing device suitable for calculating depth information based on the plurality of first tap pixel signals and the plurality of second tap pixel signals,
wherein the overflow detection circuit forms a current path from an overflow current source to a ground voltage terminal and outputs an overflow detection signal whose voltage is changed when voltages of the plurality of first tap pixel signals and voltages of the plurality of second tap pixel signals drop below a predetermined voltage.

7. The image processing system of claim 6 , wherein when the overflow detection signal has a logic low level, error data is generated in the first tap pixel or the second tap pixel, and
wherein the image processing device performs an image data process through interpolation of peripheral pixel data positioned on or near a periphery of the first tap pixel or the second tap pixel, and controls light global exposure time so that the light global exposure time is reduced until no overflow occurs.

8. The image processing system of claim 6 , wherein when the overflow detection signal has a logic high level, the image processing device is performs a process on a valid data of the first tap pixel and the second tap pixel and does not control light global exposure time.

9. The image processing system of claim 6 , wherein the overflow detection circuit detects overflow of the plurality of first tap pixel signals outputted from the plurality of first tap pixels and overflow of the plurality of second tap pixel signals outputted from the plurality of second tap pixels, performs a logic NAND operation on the plurality of first tap pixel signals and the plurality of second tap pixel signals, and outputs an overflow detection signal.

10. The image processing system of claim 6 , wherein the overflow detection circuit performs a logic NAND operation on the plurality of first tap pixel signals outputted from the plurality of first tap pixels and the plurality of second tap pixel signals outputted from the plurality of second tap pixels through a plurality of inverters connected in series to each other and NAND gates, generates a first tap overflow detection signal and a second tap overflow detection signal, performs an OR operation on the overflow detection signals through an OR gate, and outputs an overflow detection signal.

11. The image processing system of claim 10 , wherein the overflow detection circuit includes:
a first inverter group to which the plurality of first tap pixel signals are inputted, and including the plurality of inverters connected in series to each other;
a second inverter group to which the plurality of first tap pixel signals are inputted, and including the plurality of inverters connected in series to each other;
a first NAND gate suitable for receiving an output of the first inverter group through a first input terminal thereof, receiving an output of the second inverter group through a second input terminal thereof, performing the logic NAND operation on the received outputs, and generating the first tap overflow detection signal;
a third inverter group to which the plurality of second tap pixel signals are inputted, and including the plurality of inverters connected in series to each other;
a fourth inverter group to which the plurality of second tap pixel signals are inputted, and including the plurality of inverters connected in series to each other;
a second NAND gate suitable for receiving an output of the third inverter group through a first input terminal thereof, receiving an output of the fourth inverter group through a second input terminal thereof, performing the logic NAND operation on the received outputs, and generating the second tap overflow detection signal; and
an OR gate suitable for receiving the first tap overflow detection signal and the second tap overflow detection signal, performing the OR operation on the received overflow detection signals, and outputting the overflow detection signal.

12. An operating method of an image sensor, the operating method comprising:
generating first and second tap pixel signals respectively through first and second tap pixels included therein; and
detecting each voltage level of the first and second tap pixel signals to determine an overflow of at least one of the first and second tap pixels,
wherein the detecting each voltage level of the first and second tap pixel signals includes
forming of a current

Assignees

• Sk Hynix Inc

Inventors

• Lee Eun Chang
• Shin Min Seok

Classifications

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• G01S7/4913

  Circuits for detection, sampling, integration or read-out · CPC title

• H04N25/705

  Pixels for depth measurement, e.g. RGBZ · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title