Method and system for distributing keys

Patent metadata

Field	Value
Publication number	US-12413568-B2
Application number	US-202217955421-A
Country	US
Kind code	B2
Filing date	Sep 28, 2022
Priority date	Sep 28, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A method and system for distributing keys in a key distribution system includes receiving a connection for communication from a first component. A determination is made whether the first component requires a key be generated and distributed. Based upon a security mode for the communication, the key generated and distributed to the first component.

First claim

What is claimed is:

1. A method performed by a system on chip (SOC) for managing security keys, the method comprising:
detecting, via a private key distribution bus of the SoC, that a device is connected to a first component of the SoC;
in response to the detecting:
generating a key based on the device requiring the key and a security mode of the SoC, and
distributing, via the private key distribution bus of the SoC, the key to the first component; and

selectively destroying the key in response to changes associated with the security mode.

2. The method of claim 1 wherein upon the security mode being a first security mode in operation for communication, the key is generated and distributed to the first component.

3. The method of claim 1 wherein a key size is selected for generation based upon a type of the device.

4. The method of claim 2 , further comprising switching from the first security mode to a second security mode.

5. The method of claim 1 , wherein the key is selectively destroyed when the security mode changes from a secure mode to a non-secure mode.

6. The method of claim 1 , further comprising:
destroying the key when the device is disconnected.

7. The method of claim 6 , further comprising deleting an associated rule for the key generated for the first component.

8. The method of claim 1 wherein the first component includes one or more of a Peripheral Component Interconnect Express (PCIe) component, a video component, a display component or a unified memory controller component.

9. The method of claim 1 , wherein the device is a video graphics card or a network card.

10. The method of claim 1 , wherein the first component is a PCIe controller or PCIe network adapter.

11. A key distribution system, comprising:
a first module;
a private key distribution bus; and
a processor communicatively the first module via the private key distribution bus,
wherein the processor configured to:
detect, via the private key distribution bus, that a device connected to the first module,
in response to the device being detected:
generate a key based on the device requiring the key and a security mode of the processor, and
distribute, via the private key distribution bus, the key to the first module, and

selectively destroy the key in response to changes associated with the security mode.

12. The key distribution system of claim 11 wherein upon the security mode being a first security mode in operation for communication, the key is generated and distributed to the first module.

13. The key distribution system of claim 12 , further comprising the processor switching from the first security mode to a second security mode.

14. The key distribution system of claim 13 wherein the key is selectively destroyed when the security mode changes from a secure mode to a non-secure mode.

15. The key distribution system of claim 11 wherein a key size is selected for generation based upon a type of the device.

16. The key distribution system of claim 11 wherein the processor is further configured to destroy the key when the device is disconnected.

17. The key distribution system of claim 11 wherein the first module includes one or more of a Peripheral Component Interconnect Express (PCIe) component, a video component, a display component or a unified memory controller component.

18. The key distribution system of claim 11 , wherein the device is a video graphics card or a network card.

19. A non-transitory computer-readable medium for managing security keys, the non-transitory computer-readable medium having instructions recorded thereon that, when executed by a processor of a system on chip (SOC), cause the SoC to perform operations including:
detecting, via a private key distribution bus of the SoC, that a device is connected to a first component of the SoC;
in response to the detecting:
generating a key for the first component based on the device requiring the key and a security mode of the SoC, and
distributing, via the private key distribution bus of the SoC, the key to the first component; and

selectively destroying the key in response to changes associated with the security mode.

20. The non-transitory computer-readable medium of claim 19 , wherein the device is a video graphics card or a network card.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Stewart Norman Vernon Douglas
• Doctor Mihir Shaileshbhai
• Ahmed Omar Fakhri
• Jayanna Hemaprabhu
• Traver John

Classifications

• H04W12/04

  Key management, e.g. using generic bootstrapping architecture [GBA] · CPC title

• H04L63/062 Primary

  for key distribution, e.g. centrally by trusted party (cryptographic mechanisms or cryptographic arrangements for key distribution involving a central third party H04L9/0819) · CPC title