Synchronizing systems on a chip using time synchronization messages

Patent metadata

Field	Value
Publication number	US-12413325-B2
Application number	US-202117493222-A
Country	US
Kind code	B2
Filing date	Oct 4, 2021
Priority date	Oct 4, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases and an inter-SoC interface that connects the first and second SoCs. The operations of the first and second SoCs are synchronized by aligning the time bases for the SoCs using a modified PTP technique. The technique includes the second SoC receiving a time synchronization message from the first SoC over the inter-SoC interface, recording a local timestamp of receipt of the time synchronization message, receiving a master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the time synchronization message by the first SoC, and calculating a time offset between the local timestamp and the master timestamp. The time bases of the first SoC and second SoC are then aligned using the calculated time offset. To account for transmission delays, multiple time offsets may be averaged.

First claim

What is claimed is:

1. A method of synchronizing first and second systems on a chip (SoCs) of an electronic eyewear device, the first and second SoCs having independent time bases and connected by an inter-SoC interface of the electronic eyewear device, the method comprising:
physically separating the first SoC and the second SoC to provide passive cooling of the first SoC and the second SoC in physically separate regions of the electronic eyewear device;
dynamically allocating processing workload between the first SoC and the second SoC in accordance with at least one of processing requirements or temperatures of the first SoC and the second SoC;
sharing data over the inter-SoC interface for synchronous data processing of the processing workload by the first and second SoCs; and
synchronizing the data processing of the processing workload of the first and second SoCs by periodically performing operations comprising:
the second SoC receiving a time synchronization message from the first SoC over the inter-SoC interface;
the second SoC recording a local timestamp of receipt of the time synchronization message;
the second SoC receiving a master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the time synchronization message by the first SoC;
the second SoC calculating a time offset between the local timestamp and the master timestamp; and
aligning the time bases of the first SoC and the second SoC using the calculated time offset.

2. The method of claim 1 , wherein the second SoC recording the local timestamp of receipt of the time synchronization message comprises recording a local timestamp of an operating system of the second SoC.

3. The method of claim 1 , wherein the second SoC recording the local timestamp of receipt of the time synchronization message comprises generating the local timestamp using at least one of a driver, firmware, or hardware of the second SoC.

4. The method of claim 1 , wherein synchronizing the data processing of the processing workload of the first and second SoCs further comprises periodically performing operations comprising:
the second SoC sending a second time synchronization message to the first SoC over the inter-SoC interface;
the second SoC recording a second local timestamp of a time of sending the second time synchronization message; and
the second SoC receiving a second master timestamp corresponding to a timestamp recorded by the first SoC corresponding to a time of receiving the second time synchronization message by the first SoC.

5. The method of claim 4 , wherein the second SoC calculating the time offset comprises calculating 0.5*(the master timestamp+the second master timestamp−the local timestamp−the second local timestamp).

6. The method of claim 1 , wherein aligning the time bases of the first SoC and the second SoC using the calculated time offset comprises the second SoC using the time offset to adjust a timing of the second SoC to align with a timing of the first SoC.

7. The method of claim 6 , wherein adjusting the timing of the second SoC to align with the timing of the first SoC comprises smoothing timing adjustments over time to ensure that a synchronized time of the second SoC is always increasing and continuous.

8. The method of claim 1 , wherein aligning the time bases of the first SoC and the second SoC using the calculated time offset comprises the second SoC using the time offset to adjust a timing of signals received from the first SoC.

9. The method of claim 1 , further comprising:
comparing the calculated time offset to a clock drift tolerance threshold; and
when the calculated time offset exceeds or is estimated to exceed the clock drift tolerance threshold, performing the steps of:
the second SoC receiving a second time synchronization message from the first SoC over the inter-SoC interface;
the second SoC recording a second local timestamp of receipt of the second time synchronization message;
the second SoC receiving a second master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the second time synchronization message by the first SoC;
the second SoC calculating a second time offset between the second local timestamp and the second master timestamp; and
aligning the time bases of the first SoC and the second SoC using the calculated second time offset.

10. An electronic eyewear device comprising:
a first system on a chip (SoC) having a first independent time base;
a second SoC having a second independent time base, wherein the first SoC and the second SoC are physically separated to provide passive cooling of the first SoC and the second SoC in physically separate regions of the electronic eyewear device, and wherein a processing workload between the first SoC and the second SoC is dynamically allocated in accordance with at least one of processing requirements or temperatures of the first SoC and the second SoC;
an inter-SoC interface that connects the first SoC and the second SoC; and
a computer readable medium coupled with the second SoC, the computer readable medium comprising instructions stored thereon that are executable by the second SoC to cause the second SoC to perform operations for synchronizing the independent time bases of the first SoC and the second SoC, the operations performed by the second SoC including:
sharing data over the inter-SoC interface with the first SoC for synchronous data processing of the processing workload by the first and second SoCs; and
synchronizing the data processing of the processing workload of the first and second SoCs by periodically performing operations comprising:
receiving a time synchronization message from the first SoC over the inter-SoC interface;
recording a local timestamp of receipt of the time synchronization message;
receiving a master timestamp corresponding to a timestamp recorded by the first SoC corresponding to the time of sending the time synchronization message by the first SoC;
calculating a time offset between the local timestamp and the master timestamp; and
aligning the time bases of the first SoC and the second SoC using the calculated time offset.

11. The electronic eyewear device of claim 10 , wherein the inter-SoC interface comprises a Peripheral Component Interconnect Express (PCIe) formatted bus.

12. The electronic eyewear device of claim 10 , wherein the second SoC executes instructions to record a local timestamp of an operating system of the second SoC.

13. The electronic eyewear device of claim 10 , wherein the second SoC executes instructions to cause generation of the local timestamp using at least one of a driver, firmware, or hardware of the second SoC.

14. The electronic eyewear device of claim 10 , wherein the second SoC executes further instructions to cause the second SoC to synchronize the data processing of the first and second SoCs by further periodically performing operations comprising:
sending a second time synchronization message to the first SoC over the inter-SoC interface;
recording a second local timestamp of a time of sending the second time synchronization message; and
receiving a second master timestamp corresponding to a timestamp recorded by the first SoC corresponding to a time of receiving the second time synchronization message by the first SoC.

15. The electronic eyewear device of claim 14 , wherein the second SoC calculates the time offset by executing instructions to calculate 0.5*(the master timestamp+the second master timestamp−the local timestamp−the second local timestamp).

Assignees

• Ahn Samuel
• Ryuma Dmitry
• Snap Inc

Inventors

• Ahn Samuel
• Ryuma Dmitry

Classifications

• H04J3/0685

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title

• H04J3/0682

  by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging · CPC title

• G06F2213/0038

  System on Chip · CPC title

• G06F13/405

  where the bridge performs a synchronising function · CPC title

• H04J3/065 Primary

  using timestamps · CPC title