Reconfigurable analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-12413242-B2
Application number	US-202018254204-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 21, 2020
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

This disclosure describes apparatuses, methods, and techniques that enable a computing device to support a dynamic range of audio quality, varying bandwidths, varying sampling rates, numerous effective number of bits (ENOBs) resolutions, conserve power during an overall usage of the computing device, and enhance a user experience. To do so, the computing device utilizes a reconfigurable analog-to-digital converter (ADC). The reconfigurable ADC includes a successive-approximation-register (SAR) ADC, a noise-canceling circuit, and a noise-shaping circuit. The reconfigurable ADC can selectively operate in different modes of operation, in part, by enabling or disabling the noise-canceling circuit and the noise-shaping circuit.

First claim

What is claimed:

1. An apparatus comprising:
a reconfigurable analog-to-digital converter (ADC), the reconfigurable ADC configured to selectively support at least two different resolution settings, the reconfigurable ADC including:
a successive-approximation-register (SAR) ADC, the SAR ADC configured to:
perform a first cycle of an N-bit analog-to-digital conversion of an analog input voltage to generate an N-bit digital output, the N-bit analog-to-digital conversion including a conversion noise and a residual voltage after the first cycle of the N-bit analog-to-digital conversion; and
amplify a difference in the analog input voltage between two close time intervals;

a noise-canceling circuit configured to lower the conversion noise by sampling the analog input voltage after amplifying the difference in the analog input voltage; and
a noise-shaping circuit configured to add or subtract the residual voltage from the first cycle to a second cycle of the N-bit analog-to-digital conversion to reduce a quantization noise of the second cycle of the N-bit analog-to-digital conversion, the reconfigurable ADC being configured to selectively operate in one of at least two different modes of operation that comprise at least two of:
a first mode of operation, the first mode of operation configured to use the SAR ADC, the noise-canceling circuit, and the noise-shaping circuit;
a second mode of operation, the second mode of operation configured to use the SAR ADC and the noise-canceling circuit;
a third mode of operation, the third mode of operation configured to use the SAR ADC and the noise-canceling circuit; and
a fourth mode of operation, the fourth mode of operation configured to use the SAR ADC.

2. The apparatus of claim 1 , wherein the residual noise is a first residual noise of the first cycle of the N-bit analog-to-digital conversion, the second cycle of N-bit analog-to-digital conversion includes a second residual voltage, and wherein the reconfigurable ADC is configured to utilize the noise-shaping circuit to:
weight the first residual voltage from the first cycle and the second residual voltage from the second cycle; and
add or subtract the weighted residual voltages from the first and the second cycle to a third cycle of the N-bit analog-to-digital conversion, further reducing the quantization of the third cycle of the N-bit analog-to-digital conversion.

3. The apparatus of claim 2 , wherein:
a resolution of the at least two different resolution settings is measured or calculated in effective number of bits (ENOBs);
the conversion noise comprises a value that is approximately equal to a Boltzmann constant (k) multiplied by a period of a sampling time (T) and divided by a sampling capacitance (C); and
the first and the second residual voltages comprise a difference between an output voltage of a digital-to-analog converter (DAC) and the analog input voltage.

4. The apparatus of claim 3 , wherein the SAR ADC includes:
a comparator;
a logic block configured to output the N-bit digital output and an output voltage of the DAC;
a capacitive DAC (CDAC) utilizing a capacitance array; and
a preamplifier with a gain A coupled between a common terminal of the capacitance array and the comparator, wherein the preamplifier is configured to amplify the difference in the analog input voltage between two close time intervals.

5. The apparatus of claim 4 , wherein the noise-canceling circuit includes:
a first capacitor having a first and a second terminal, and wherein:
the second terminal of the first capacitor coupled to an output of the preamplifier; and
the first terminal of the first capacitor coupled between the preamplifier and the comparator;

a common-mode voltage; and
a first switch having a first and a second terminal, and wherein:
the first terminal of the first switch coupled to the common-mode voltage; and
the second terminal of the first switch coupled to the first terminal of the first capacitor.

6. The apparatus of claim 5 , wherein the noise-shaping circuit includes:
an amplifier having a first input, a second input, and an output;
a second switch having a first and a second terminal;
a third switch having a first and a second terminal;
a fourth switch having a first and a second terminal;
a fifth switch having a first and a second terminal; and
a second capacitor having a first and a second terminal.

7. The apparatus of claim 6 , wherein:
the first terminal of the second switch is coupled to the output of the amplifier and the first terminal of the fifth switch;
the second terminal of the second switch is coupled to the first terminal of the fourth switch and the second terminal of the second capacitor;
the second terminal of the fourth switch is coupled to a first input of the comparator, the first terminal of the first capacitor, and the first input of the amplifier;
the first terminal of the second capacitor is coupled to the second terminal of the fifth switch and the second terminal of the third switch; and
the first terminal of the third switch is coupled to the common-mode voltage and the first terminal of the first switch.

8. The apparatus of claim 1 , wherein the reconfigurable ADC is configured to selectively operate in:
the first mode by operating in a first phase, a second phase, a comparator phase, a first residual phase, and a second residual phase;
the second mode by operating in the first phase, the second phase, and the comparator phase;
the third mode by operating in the first phase, the second phase, and the comparator phase; and
the fourth mode by operating in first phase and the comparator phase.

9. The apparatus of claim 8 , wherein the reconfigurable ADC is configured to selectively support the at least two different resolution settings by consuming at least two different amounts of power, supporting at least two different bandwidths, and operating in at least two different sampling rates.

10. The apparatus of claim 9 , wherein:
the at least two different resolution settings include a first, a second, a third, and a fourth ENOB resolution, and wherein:
the first ENOB resolution is higher than the second ENOB resolution;
the second ENOB resolution is higher than the third ENOB resolution; and
the third ENOB resolution is higher than the fourth ENOB resolution;

the at least two different amounts of power include a first, a second, a third, and a fourth amount of power, and wherein:
the first amount of power is higher than the second amount of power;
the second amount of power is higher than the third amount of power; and
the third amount of power being is than the fourth amount of power;

the at least two different bandwidths include a first and a second bandwidth, and wherein:
the first bandwidth is higher than the second bandwidth; and

the at least two different sampling rates include a first and a second sampling rate, and wherein:
the first sampling rate is considerably larger than a Nyquist rate; and
the second sampling rate is approximately equal to the Nyquist rate.

11. The apparatus of claim 10 , wherein the reconfigurable ADC is configured to selectively operate in:
the first mode, the first mode supporting the first ENOB resolution, consuming the first amount of power, supporting the first bandwidth, and operating in the first sampling rate;
the second mode, the second mode supporting the second ENOB resolution, consuming the second amount of power, supporting the first bandwidth, and operating in the first sampling rate;
the third mode, the third mode supporting the third ENOB resolution, consuming the third amount of power, supporting the first bandwidth, and operating

Assignees

• Google Llc

Inventors

• Sankaragomathi Kannan Aryaperumal
• Vanderhaegen Johan Peter

Classifications

• H03M3/498

  Variable sample rate · CPC title

• H03M1/16

  with scale factor modification, i.e. by changing the amplification between the steps {(H03M1/141 takes precedence)} · CPC title

• H03M1/0854

  of quantisation noise · CPC title

• H03M1/008

  among different conversion characteristics, e.g. between mu-255 and a-laws · CPC title

• H03M1/007

  among different resolutions · CPC title