Pixel array package structure and display panel

US12412874B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12412874-B2
Application numberUS-202318460673-A
CountryUS
Kind codeB2
Filing dateSep 4, 2023
Priority dateAug 22, 2018
Publication dateSep 9, 2025
Grant dateSep 9, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel array package structure includes: a substrate; a pixel array disposed on the substrate, in which the pixel array includes a plurality of light emitting diode chips, and the light emitting diode chips include at least one red diode chip, at least one green diode chip, at least one blue diode chip, and a combination thereof; a reflective layer disposed on the substrate and between any two adjacent of the light emitting diode chips; a light-absorbing layer disposed on the reflective layer and surrounding the pixel array; and a light-transmitting layer disposed on the pixel array, the reflective layer, and the light-absorbing layer, in which the light-transmitting layer has an upper surface and a lower surface opposite thereto, and the lower surface is in contact with the pixel array, and the upper surface has a roughness of 0.005 mm to 0.1 mm.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel array package structure, comprising: a substrate; a pixel array disposed on the substrate, wherein the pixel array comprises a plurality of light emitting diode chips, and the plurality of light emitting diode chips comprise a red diode chip, a green diode chip, a blue diode chip, and a combination thereof; a reflective layer disposed on the substrate and between any two adjacent of the plurality of light emitting diode chips; a light-absorbing layer embedded in the reflective layer and surrounding the pixel array; and a light-transmitting layer disposed on the pixel array, the reflective layer, and the light-absorbing layer, wherein the light-transmitting layer has an upper surface and a lower surface opposite thereto, and the lower surface is in contact with the pixel array. 2. The pixel array package structure of claim 1 , further comprising an anti-external light material disposed on the light-transmitting layer. 3. The pixel array package structure of claim 2 , wherein the anti-external light material is a polarizer. 4. The pixel array package structure of claim 1 , wherein the reflective layer is composed of a mixture of a colloidal material and inorganic particles, wherein the inorganic particles comprise titanium dioxide, boron nitride, silicon dioxide, barium sulfate or aluminum oxide. 5. The pixel array package structure of claim 1 , wherein an upper surface of the light-absorbing layer is substantially coplanar with an upper surface of the pixel array. 6. The pixel array package structure of claim 1 , wherein the light-absorbing layer is composed of a colloidal material and an inorganic material, or a colloidal material and an organic material. 7. The pixel array package structure of claim 6 , wherein the inorganic material is carbon powder or perovskite. 8. The pixel array package structure of claim 7 , wherein the carbon powder has a specific surface area of 50 m 2 /g to 70 m 2 /g. 9. A display panel, comprising: a plurality of sub-display panels, any two adjacent of the sub-display panels having a splicing gap, wherein each of the sub-display panels comprises a plurality of the pixel array package structures of claim 1 . 10. The display panel of claim 9 , further comprising an anti-external light material disposed on the light-transmitting layer. 11. The display panel of claim 10 , wherein the anti-external light material is a polarizer. 12. The display panel of claim 9 , wherein the reflective layer is composed of a mixture of a colloidal material and inorganic particles, wherein the inorganic particles comprise titanium dioxide, boron nitride, silicon dioxide, barium sulfate or aluminum oxide. 13. The display panel of claim 9 , wherein an upper surface of the light-absorbing layer is substantially coplanar with an upper surface of the pixel array. 14. The display panel of claim 9 , wherein the light-absorbing layer is composed of a colloidal material and an inorganic material, or a colloidal material and an organic material. 15. The display panel of claim 14 , wherein the inorganic material is carbon powder or perovskite. 16. The display panel of claim 15 , wherein the carbon powder has a specific surface area of 50 m 2 /g to 70 m 2 /g. 17. The display panel of claim 9 , wherein the splicing gap between the sub-display panels is less than 100 μm. 18. The display panel of claim 9 , wherein any two adjacent of the pixel array package structures have a pitch therebetween. 19. The display panel of claim 18 , wherein the LED chips in the pixel array package structure are micro LEDs, the pitch between the pixel array package structures is less than 0.5 mm. 20. The display panel of claim 18 , wherein the LED chips in the pixel array package structure are mini LEDs, the pitch between the pixel array package structures is about 0.5 mm to 1.0 mm.

Assignees

Inventors

Classifications

  • H10W90/00Primary

    Package configurations · CPC title

  • Arrangements for polarized light emission (H10K50/86 takes precedence) · CPC title

  • comprising reflective means · CPC title

  • comprising light absorbing layers, e.g. light-blocking layers · CPC title

  • Arrangements for polarized light emission (H10K59/8791 takes precedence) · CPC title

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Frequently asked questions

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What does patent US12412874B2 cover?
A pixel array package structure includes: a substrate; a pixel array disposed on the substrate, in which the pixel array includes a plurality of light emitting diode chips, and the light emitting diode chips include at least one red diode chip, at least one green diode chip, at least one blue diode chip, and a combination thereof; a reflective layer disposed on the substrate and between any two…
Who is the assignee on this patent?
Lextar Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 09 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).