Method of reducing program disturbance in memory device and memory device utilizing same

Patent metadata

Field	Value
Publication number	US-12412609-B2
Application number	US-202318139316-A
Country	US
Kind code	B2
Filing date	Apr 25, 2023
Priority date	Dec 9, 2019
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of memory strings, one of the memory strings comprising memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells; and
a peripheral circuit coupled to the memory strings and configured to, in a pre-pulse period of a program operation:
maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell;
before applying the second voltage to the dummy word line to turn off the dummy cell, apply a sixth voltage to the dummy word line to turn on the dummy cell; and
after applying the second voltage to the dummy word line, apply a third voltage to the select line to turn off the select transistor.

2. The memory device of claim 1 , wherein:
the second voltage is substantially equal to the third voltage.

3. The memory device of claim 1 , wherein:
the first voltage is higher than each of the second voltage and the third voltage.

4. The memory device of claim 1 , wherein:
the peripheral circuit is further configured to maintain a fourth voltage on the bit line during the on-state of the select transistor, the fourth voltage being higher than each of the second voltage and the third voltage.

5. The memory device of claim 4 , wherein:
the peripheral circuit is configured to, in the pre-pulse period after applying the third voltage to the select line to turn off the select transistor, apply a fifth voltage to the bit line, the fifth voltage being lower than the fourth voltage.

6. The memory device of claim 5 , wherein:
the bit line is an unselected bit line.

7. The memory device of claim 1 , wherein:
the peripheral circuit is configured to, before applying the second voltage to the dummy word line, apply a fourth voltage to the bit line and the first voltage to the select line to turn on the select transistor.

8. The memory device of claim 7 , wherein:
the fourth voltage, the first voltage, and the sixth voltage are substantially identical.

9. The memory device of claim 1 , wherein:
the peripheral circuit is configured to, after applying the second voltage to the dummy word line, hold the second voltage on the dummy word line to retain an off-state of the dummy cell before a program period of the program operation.

10. The memory device of claim 1 , wherein:
each of the memory cells is coupled to a word line; and
in a program period of the program operation, the peripheral circuit is configured to apply a programming voltage to a selected word line from the word lines, and apply a pass voltage to an unselected word line other than the selected word line, the selected word line being coupled to a target memory cell, and the programming voltage being higher than the pass voltage.

11. The memory device of claim 10 , wherein:
the program period is after the pre-pulse period.

12. The memory device of claim 10 , wherein:
in the program period before applying the programming voltage to the selected word line, the peripheral circuit is further configured to apply the pass voltage to the selected word line.

13. The memory device of claim 10 , wherein:
The peripheral circuit is configured to, in the program period, apply a dummy voltage to the dummy word line, the dummy voltage being higher than the second voltage.

14. The memory device of claim 10 , wherein:
the peripheral circuit is configured to, in the program period, apply a supply voltage to the bit line for program inhibition.

15. The memory device of claim 10 , wherein:
the peripheral circuit is configured to, in the program period, apply a ground voltage to the bit line of the program operation.

16. A memory device, comprising:
a plurality of memory strings, one of the memory strings comprising memory cells, a select transistor coupled to a bit line and a select line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells; and
a peripheral circuit coupled to the memory strings and configured to, before programming a target memory cell of the memory cells:
apply a first voltage to the select line to turn on the select transistor, and a second voltage to the dummy word line to turn on the dummy cell; and
after applying a third voltage to the dummy word line to turn off the dummy cell, apply a fourth voltage to the select line to turn off the select transistor, the third voltage being applied after the second voltage,
wherein:
the third voltage is lower than the second voltage; and
the fourth voltage is lower than the first voltage.

17. The memory device of claim 16 , wherein before programming the target memory cell, the peripheral circuit is further configured to:
maintain a fifth voltage on the bit line before the fourth voltage is applied to the select line; and
after the fourth voltage is applied to the select line, apply a sixth voltage to the bit line, the sixth voltage being lower than the fifth voltage.

18. The memory device of claim 16 , wherein:
the first voltage is substantially equal to the second voltage; and
the third voltage is substantially equal to the fourth voltage.

19. The memory device of claim 16 , wherein:
the first voltage to the select line and the second voltage to the dummy word line are applied in a parallel manner.

20. A method of operating a memory device, wherein:
the memory device comprises a plurality of memory strings, one of the memory strings comprising memory cells, a select transistor coupled to a bit line and a select line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells; and
the method comprises:
applying a first voltage to the select line to turn on the select transistor, and a second voltage to the dummy word line to turn on the dummy cell; and
after applying a third voltage to the dummy word line to turn off the dummy cell, applying a fourth voltage to the select line to turn off the select transistor, comprising starting to apply the third voltage to the dummy word line while the first voltage is still being applied to the select line, the third voltage being lower than the second voltage, and the fourth voltage being lower than the first voltage.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Li Shan
• You Kaikai
• Cui Ying
• Jia Jianquan
• Li Kaiwei
• Zhang An

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title