Pixel circuit and display device having the same

Patent metadata

Field	Value
Publication number	US-12412509-B2
Application number	US-202318325430-A
Country	US
Kind code	B2
Filing date	May 30, 2023
Priority date	Aug 9, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A pixel circuit includes a light emitting element, a write transistor configured to write a data voltage in response to a write gate signal, a driving transistor configured to generate a driving current based on the data voltage and to apply the driving current to the light emitting element, a compensation transistor configured to diode-connect the driving transistor in response to a compensation gate signal, a first initialization transistor configured to apply a first initialization voltage to a control electrode of the driving transistor in response to an initialization gate signal, and a second initialization transistor configured to apply a second initialization voltage to an anode electrode of the light emitting element in response to a bias gate signal having an activation period longer than at least one of the compensation gate signal and the initialization gate signal.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a light emitting element;
a write transistor configured to write a data voltage in response to a write gate signal;
a driving transistor configured to generate a driving current based on the data voltage and to apply the driving current to the light emitting element;
a compensation transistor configured to diode-connect the driving transistor in response to a compensation gate signal,
wherein the compensation gate signal is different from the write gate signal, and an activation period of the compensation gate signal begins before an activation period of the write gate signal;
a first initialization transistor configured to apply a first initialization voltage to a control electrode of the driving transistor in response to an initialization gate signal; and
a second initialization transistor configured to apply a second initialization voltage to an anode electrode of the light emitting element in response to a bias gate signal having an activation period longer than at least one of the activation period of the the compensation gate signal and an activation period of the initialization gate signal,
wherein a portio nof the activation period of the compensation gate signal overlaps a portion of the activation period of the initialization gate signal, and the activation period of the bias gate signal is longer than the overlapping portions.

2. The pixel circuit of claim 1 , wherein the activation period of the bias gate signal is greater than or equal to about 480 microseconds.

3. The pixel circuit of claim 1 , further comprising:
a first emission transistor configured to apply a first power voltage to the driving transistor in response to an emission signal; and
a second emission transistor configured to transmit the driving current to the light emitting element in response to the emission signal.

4. The pixel circuit of claim 3 , wherein the bias gate signal has the activation period in an inactivation period of the emission signal.

5. The pixel circuit of claim 4 , wherein the bias gate signal has the activation period after about 2 microseconds or more passes from when the emission signal is inactivated.

6. The pixel circuit of claim 3 , wherein the emission signal is generated based on an emission clock signal, and
wherein the emission signal has an activation period of N clock times of the emission clock signal, where N is a positive integer greater than 2.

7. The pixel circuit of claim 6 , wherein the activation period of the bias gate signal is shorter than the N clock times of the emission clock signal.

8. The pixel circuit of claim 1 , wherein the activation period of each of the initialization gate signal, the compensation gate signal, and the write gate signal is within the activation period of the bias gate signal.

9. The pixel circuit of claim 1 , wherein the activation period of the initialization gate signal is within the activation period of the bias gate signal,
wherein the activation period of the write gate signal is within an inactivation period of the bias gate signal, and
wherein the compensation gate signal is activated in the activation period of the bias gate signal and is inactivated in the inactivation period of the bias gate signal.

10. The pixel circuit of claim 1 , wherein the initialization gate signal and the compensation gate signal are activated in an inactivation period of the bias gate signal, and are inactivated in the activation period of the bias gate signal, and
wherein the activation period of the write gate signal is within the activation period of the bias gate signal.

11. A display device, comprising:
a display panel comprising a plurality of pixel circuits;
a data driver configured to provide a data voltage to each of the pixel circuits;
a gate driver configured to provide a write gate signal, a compensation gate signal, an initialization gate signal, and a bias gate signal to each of the pixel circuits; and
a timing controller configured to control the data driver and the gate driver,
wherein each of the pixel circuits comprises:
a light emitting element;
a write transistor configured to write the data voltage in response to the write gate signal;
a driving transistor configured to generate a driving current based on the data voltage and to apply the driving current to the light emitting element;
a compensation transistor configured to diode-connect the driving transistor in response to the compensation gate signal,
wherein the compensation gate signal is different from the write gate signal, and an activation period of the compensation gate signal begins before an activation period of the write gate signal;
a first initialization transistor configured to apply a first initialization voltage to a control electrode of the driving transistor in response to the initialization gate signal; and
a second initialization transistor configured to apply a second initialization voltage to an anode electrode of the light emitting element in response to the bias gate signal having an activation period longer than at least one of the activation period of the compensation gate signal and an activation period of the initialization gate signal,
wherein a portion of the activation period of the compensation gate signal overlaps a portion of the activation period of the initialization gate signal, and the activation period of the bias gate signal is longer than the overlapping portions.

12. The display device of claim 11 , wherein the activation period of the bias gate signal is greater than or equal to about 480 microseconds.

13. The display device of claim 11 , further comprising:
an emission driver configured to provide an emission signal to each of the pixel circuits,
wherein each of the pixel circuits further comprises:
a first emission transistor configured to apply a first power voltage to the driving transistor in response to the emission signal; and
a second emission transistor configured to transmit the driving current to the light emitting element in response to the emission signal.

14. The display device of claim 13 , wherein the bias gate signal has the activation period in an inactivation period of the emission signal.

15. The display device of claim 14 , wherein the bias gate signal has the activation period after about 2 microseconds or more passes from when the emission signal is inactivated.

16. The display device of claim 13 , wherein the emission signal is generated based on an emission clock signal, and
wherein the emission signal has an activation period of N clock times of the emission clock signal, where N is a positive integer greater than 2.

17. The display device of claim 16 , wherein the activation period of the bias gate signal is shorter than the N clock times of the emission clock signal.

18. The display device of claim 11 , wherein the activation period of each of the initialization gate signal, the compensation gate signal, and the write gate signal is within the activation period of the bias gate signal.

19. The display device of claim 11 , wherein the activation period of the initialization gate signal is within the activation period of the bias gate signal,
wherein the activation period of the write gate signal is within an inactivation period of the bias gate signal, and
wherein the compensation gate signal is activated in the activation period of the bias gate signal and is inactivated in the inactivation period of the bias gate signal.

20. The display devi

Assignees

• Samsung Display Co Ltd

Inventors

• Kwon Semyung
• Bae Injun
• Jung Sugwoo

Classifications

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G2310/061

  for resetting or blanking · CPC title