Native sampler feedback technology

Patent metadata

Field	Value
Publication number	US-12412332-B2
Application number	US-202117485244-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

Methods, systems and apparatuses may provide for hardware sampler technology that determines mip region dimensions of a feedback map based on a description of the feedback map, identifies accessed texels in a texture based on a view of a resource that is paired with the feedback map, and records the accessed texels in the feedback map based on the mip region dimensions.

First claim

We claim:

1. A computing system comprising:
a host processor; and
a graphics processor coupled to the host processor, wherein the graphics processor includes sampler logic coupled to one or more substrates, the sampler logic to:
determine mip region dimensions of a feedback map based on a description of the feedback map, identify accessed texels in a texture based on a view of a resource that is paired with the feedback map, and record the accessed texels in the feedback map based on the mip region dimensions;
wherein the graphics processor further includes a native copy operation to transfer mip region information between the feedback map and an application resource, wherein the native copy operation is to operate via one or more of:
bypassing a padded portion of the feedback map, or
bypassing, by the mip region information, a color compression surface.

2. The computing system of claim 1 , wherein the sampler logic is to
translate coordinates of the accessed texels into mip region coordinates in the feedback map based on the mip region dimensions, and wherein the accessed texels are recorded in the feedback map in accordance with the mip region coordinates.

3. The computing system of claim 1 , wherein each pixel in the feedback map is to contain information for one complete mip region.

4. The computing system of claim 1 , wherein the accessed texels are recorded in the feedback map in an application-usable data storage layout.

5. The computing system of claim 1 , wherein the view is a subset of all array elements of the resource.

6. The computing system of claim 1 , wherein the view is a subset of all mip levels of the resource.

7. The computing system of claim 1 , wherein the view is to be a shader resource view.

8. A semiconductor apparatus comprising:
one or more substrates; and
sampler logic coupled to the one or more substrates, wherein the sampler logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the sampler logic to:
determine mip region dimensions of a feedback map based on a description of the feedback map;
identify accessed texels in a texture based on a view of a resource that is paired with the feedback map; and
record the accessed texels in the feedback map based on the mip region dimensions;
wherein the semiconductor apparatus further includes a native copy operation to transfer mip region information between the feedback map and an application resource, wherein the native copy operation is to operate via one or more of:
bypassing a padded portion of the feedback map, or
bypassing, by the mip region information, a color compression surface.

9. The semiconductor apparatus of claim 8 , wherein the sampler logic is to translate coordinates of the accessed texels into mip region coordinates in the feedback map based on the mip region dimensions, and wherein the accessed texels are recorded in the feedback map in accordance with the mip region coordinates.

10. The semiconductor apparatus of claim 8 , wherein each pixel in the feedback map is to contain information for one complete mip region.

11. The semiconductor apparatus of claim 8 , wherein the accessed texels are recorded in the feedback map in an application-usable data storage layout.

12. The semiconductor apparatus of claim 8 , wherein the view is a subset of all array elements of the resource.

13. The semiconductor apparatus of claim 8 , wherein the view is a subset of all mip levels of the resource.

14. The semiconductor apparatus of claim 8 , wherein the view is to be a shader resource view.

15. A method comprising:
determining, by a hardware sampler of a graphics processor, mip region dimensions of a feedback map based on a description of the feedback map;
identifying, by the hardware sampler, accessed texels in a texture based on a view of a resource that is paired with the feedback map; and
recording, by the hardware sampler, the accessed texels in the feedback map based on the mip region dimensions;
wherein the graphics processor further includes a native copy operation to transfer mip region information between the feedback map and an application resource, wherein the native copy operation operates via one or more of:
bypassing a padded portion of the feedback map, or
bypassing, by the mip region information, a color compression surface.

16. The method of claim 15 , further including translating, by the hardware sampler, coordinates of the accessed texels into mip region coordinates in the feedback map based on the mip region dimensions, wherein the accessed texels are recorded in the feedback map in accordance with the mip region coordinates.

17. The method of claim 15 , wherein each pixel in the feedback map contains information for one complete mip region.

18. The method of claim 15 , wherein the accessed texels are recorded in the feedback map in an application-usable data storage layout.

19. The method of claim 15 , wherein the view is a subset of all array elements of the resource.

20. The method of claim 15 , wherein the view is a subset of all mip levels of the resource.

21. The method of claim 15 , wherein the view is a shader resource view.

Assignees

• Intel Corp

Inventors

• Johnston Daniel
• Harel Yoav
• Dasgupta Subhajit

Classifications

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/04 Primary

  Texture mapping · CPC title