Effective metal density screens for hierarchical design rule checking (DRC) analysis

Patent metadata

Field	Value
Publication number	US-12412020-B2
Application number	US-202217666635-A
Country	US
Kind code	B2
Filing date	Feb 8, 2022
Priority date	Feb 8, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of effective metal density screens during hierarchical design rule checking (DRC) analysis. A non-limiting example computer-implemented method includes providing a first hierarchical level of a chip design. The first hierarchical level includes one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design. A tuple is assigned to the blockage shape. The tuple includes a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape. The method includes determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape and the maximum expected density for the blockage shape.

First claim

What is claimed is:

1. A computer-implemented method comprising:
providing a first hierarchical level of a chip design, the first hierarchical level comprising one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design, the internal structure unknown to the first hierarchical level;
assigning, to the blockage shape, a tuple comprising a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape; and
determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape violating a maximum density limit for the chip design or the maximum expected density for the blockage shape violating a minimum density limit for the chip design, thereby detecting the density violation prior to executing a design rule check (DRC) for the second hierarchical level.

2. The computer-implemented method of claim 1 further comprising adjusting one or more of a size, a shape, and a position of an internal shape of the one or more internal shapes of the first hierarchical level in response to determining that the density violation exists.

3. The computer-implemented method of claim 2 , wherein the adjustment is made prior to completing a design rule check of the second hierarchical level.

4. The computer-implemented method of claim 1 , wherein the first hierarchal level comprises a child level of the chip design and the second hierarchical level comprises a parent level of the child level.

5. The computer-implemented method of claim 1 , wherein the first hierarchal level comprises a first child level of the chip design and the second hierarchical level comprises a second child level of the chip design.

6. The computer-implemented method of claim 1 , wherein the internal shapes comprise wire shapes and fill shapes.

7. The computer-implemented method of claim 1 , wherein the assigned values for the minimum expected density and the maximum expected density are defined by a design rule checking (DRC) deck minimum density requirement and a maximum density requirement, respectively.

8. A system comprising a memory having computer readable instructions and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
providing a first hierarchical level of a chip design, the first hierarchical level comprising one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design, the internal structure unknown to the first hierarchical level;
assigning, to the blockage shape, a tuple comprising a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape; and
determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape violating a maximum density limit for the chip design or the maximum expected density for the blockage shape violating a minimum density limit for the chip design, thereby detecting the density violation prior to executing a design rule check (DRC) for the second hierarchical.

9. The system of claim 8 further comprising adjusting one or more of a size, a shape, and a position of an internal shape of the one or more internal shapes of the first hierarchical level in response to determining that the density violation exists.

10. The system of claim 9 , wherein the adjustment is made prior to completing a design rule check of the second hierarchical level.

11. The system of claim 8 , wherein the first hierarchal level comprises a child level of the chip design and the second hierarchical level comprises a parent level of the child level.

12. The system of claim 8 , wherein the first hierarchal level comprises a first child level of the chip design and the second hierarchical level comprises a second child level of the chip design.

13. The system of claim 8 , wherein the internal shapes comprise wire shapes and fill shapes.

14. The system of claim 8 , wherein the assigned values for the minimum expected density and the maximum expected density are defined by a design rule checking (DRC) deck minimum density requirement and a maximum density requirement, respectively.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
providing a first hierarchical level of a chip design, the first hierarchical level comprising one or more internal shapes and at least one blockage shape having an internal structure defined at a second hierarchical level of the chip design, the internal structure unknown to the first hierarchical level;
assigning, to the blockage shape, a tuple comprising a metal layer identifier for the blockage shape, a minimum expected density for the blockage shape, and a maximum expected density for the blockage shape; and
determining whether a density violation exists in the first hierarchical level based in part on one or both of the minimum expected density for the blockage shape violating a maximum density limit for the chip design or the maximum expected density for the blockage shape violating a minimum density limit for the chip design, thereby detecting the density violation prior to executing a design rule check (DRC) for the second hierarchical.

16. The computer program product of claim 15 further comprising adjusting one or more of a size, a shape, and a position of an internal shape of the one or more internal shapes of the first hierarchical level in response to determining that the density violation exists.

17. The computer program product of claim 16 , wherein the adjustment is made prior to completing a design rule check of the second hierarchical level.

18. The computer program product of claim 15 , wherein the first hierarchal level comprises a child level of the chip design and the second hierarchical level comprises a parent level of the child level.

19. The computer program product of claim 15 , wherein the first hierarchal level comprises a first child level of the chip design and the second hierarchical level comprises a second child level of the chip design.

20. The computer program product of claim 15 , wherein the internal shapes comprise wire shapes and fill shapes.

Assignees

• IBM

Inventors

• Veraa Brian
• Kruse Ryan Michael
• Gonzalez Christopher
• Wolpert David

Classifications

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title