Memory system with cached memory module operations

Patent metadata

Field	Value
Publication number	US-12411781-B2
Application number	US-202318513246-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Oct 1, 2015
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.

First claim

We claim:

1. A memory controller, comprising:
an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space, at least a portion of the DRAM storage space configured as a cache for the SCM storage space, the interface to receive an incoming tag address for a read operation;
tag comparison circuitry to perform a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache; and
wherein the data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.

2. The memory controller of claim 1 , wherein the interface comprises:
a first half-width channel interface to carry out a first transaction along a first channel; and
a second half-width channel interface to carry out a second transaction along a second channel, the second transaction independent of the first transaction.

3. The memory controller of claim 1 , wherein the interface comprises:
a full-width lockstep channel interface.

4. The memory controller of claim 1 , wherein:
the interface is to couple to a hybrid memory module that comprises the storage class memory (SCM) space and the dynamic random access memory (DRAM) space.

5. The memory controller of claim 1 , wherein:
the interface is to couple to a first memory module that comprises the storage class memory (SCM) space and a second memory module that comprises the dynamic random access memory (DRAM) space.

6. The memory controller of claim 5 , wherein:
the interface is to couple to the first memory module and the second memory module via respective point-to-point signaling links.

7. The memory controller of claim 5 , wherein:
the interface is to couple to the first memory module and the second memory module via a multi-drop signaling link.

8. The memory controller of claim 1 , wherein the incoming tag address is error coded with error information via an error detection code (EDC), and wherein:
the tag comparison circuitry comprises error detection circuitry (EDC) to decode the error information from the incoming tag address.

9. A method of operation in a memory controller, the method comprising:
requesting an address for a read operation from dynamic random access memory (DRAM) storage space, at least a portion of the DRAM storage space configured as a DRAM cache for storage class memory (SCM) storage space;
receiving the address as an incoming tag address from the DRAM storage space;
performing a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache; and
directly receiving, conditionally, first data from the addressed DRAM cache space based on the results of the comparison.

10. The method of claim 9 , wherein the directly receiving, conditionally, comprises:
directly receiving the first data from the addressed cache space when the comparison indicates a match between the incoming tag address and the stored tag addresses.

11. The method of claim 10 , wherein the directly receiving, conditionally, comprises:
when the comparison indicates a mismatch between the incoming tag address from the DRAM cache and the stored tag addresses, dispatching a read command with the address to the SCM storage space to retrieve second data;
receiving the second data as read data from the addressed SCM storage space.

12. The method of claim 9 , wherein:
the requesting of the address for the read operation is carried out via a request interface that couples to a hybrid memory module that comprises the storage class memory (SCM) space and the dynamic random access memory (DRAM) space.

13. The method of claim 9 , wherein:
the requesting of the address for the read operation is carried out via a request interface that couples to a first memory module that comprises the storage class memory (SCM) space and a second memory module that comprises the dynamic random access memory (DRAM) space.

14. The method of claim 13 , wherein:
the requesting of the address for the read operation by the request interface is sent to the first memory module and the second memory module via respective point-to-point signaling links.

15. The method of claim 13 , wherein:
the requesting of the address for the read operation by the request interface is sent to the first memory module and the second memory module via a multi-drop signaling link.

16. An integrated circuit (IC) chip, comprising:
memory control circuitry, comprising:
interface circuitry to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space, at least a portion of the DRAM storage space configured as a cache for the SCM storage space, the interface to receive an incoming address for a read operation;
tag comparison circuitry to perform a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache; and
wherein the data is received as read data directly from the addressed DRAM cache space when the comparison indicates a match between the incoming tag address and the stored tag addresses; and
wherein the data is received as read data from a subsequently accessed portion of the SCM storage space that corresponds to the tag address when the comparison indicates a mismatch between the incoming tag address from the DRAM cache and the stored tag addresses.

17. The IC chip of claim 16 , wherein the interface circuitry comprises:
a first half-width channel interface to carry out a first transaction along a first channel; and
a second half-width channel interface to carry out a second transaction along a second channel, the second transaction independent of the first transaction.

18. The IC chip of claim 16 , wherein the interface circuitry comprises:
a full-width lockstep channel interface.

19. The IC chip of claim 16 , wherein:
the interface circuitry is to couple to a hybrid memory module that comprises the storage class memory (SCM) space and the dynamic random access memory (DRAM) space.

20. The IC chip of claim 16 , wherein:
the interface circuitry is to couple to a first memory module that comprises the storage class memory (SCM) space and a second memory module that includes the dynamic random access memory (DRAM) space.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Wright Kenneth L
• Linstadt John Eric
• Hampel Craig

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F2212/403

  Error protection encoding, e.g. using parity or ECC codes · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title