Apparatus for processor with hardware fence and associated methods

Patent metadata

Field	Value
Publication number	US-12411693-B2
Application number	US-202017138841-A
Country	US
Kind code	B2
Filing date	Dec 30, 2020
Priority date	Dec 30, 2020
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

An apparatus includes a pipelined processor. The pipelined processor includes a pipeline and a hardware fence. The hardware fence detects if a hazard condition exists by comparing an address for an input operation with an address for an output operation.

First claim

The invention claimed is:

1. An apparatus, comprising:
a pipelined processor comprising branched parallel processing paths for instructions, and a hardware fence that maintains increasing transaction identifications (IDs) representing a submitted order on when instructions enter and are being processed within the branched parallel processing paths, wherein the increasing transaction IDs representing the submitted order are checked at a pipeline element level to stall a pipeline element when advancement of a pipeline stage of the branched parallel processing paths would produce an erroneous result.

2. The apparatus according to claim 1 , wherein the increasing transaction IDs can be used to determine when a transaction for a stage representing part of an instruction results in a hazard by comparing an address for an input operation with an address for an output operation, wherein the input operation comprises a read operation.

3. The apparatus according to claim 2 , wherein a hazard condition exists where a later read operation has an address specified that matches an address specified for an earlier write operation.

4. The apparatus according to claim 2 , wherein the output operation comprises a write operation.

5. The apparatus according to claim 4 , wherein the hardware fence comprises a comparator to compare the address specified for the read operation with the address specified for the write operation based on a pipeline memory element.

6. The apparatus according to claim 1 , wherein the pipelined processor comprises a first-in first-out (FIFO) circuit, and wherein the hardware fence detects if a hazard condition exists by comparing an address for an input operation with an address for an output operation, wherein the input and output operations are stored in the FIFO circuit.

7. The apparatus according to claim 1 , wherein the pipelined processor is stalled if the hardware fence detects that a hazard condition exists.

8. The apparatus according to claim 1 , wherein the hardware fence uses modulo IDs to implement the increasing transaction IDs.

9. The apparatus according to claim 1 , wherein the pipelined processor comprises a cache, and wherein a partial hardware fence is used with the cache.

10. An apparatus, comprising:
a pipelined processor integrated into an integrated circuit, the pipelined processor comprising:
branched parallel processing paths for instructions supplied to the pipeline processor; and
a hardware fence that maintains increasing transaction identifications (IDs) representing a submitted order on when instructions supplied to the pipeline processor enter and are being processed within the branched parallel processing paths,
wherein the increasing transaction IDs are checked at a pipeline element level to stall a pipeline element when advancement of a pipeline stage of the branched parallel processing paths would produce an erroneous result.

11. The apparatus according to claim 10 , wherein the pipelined processor is stalled if the hardware fence detects that a hazard condition exists.

12. The apparatus according to claim 10 , wherein the hardware fence uses modulo IDs to implement the increasing transaction IDs.

13. The apparatus according to claim 12 , wherein the hardware fence comprises an adder or a subtracter to receive modulo IDs and to generate an output whether a first instruction occurs before a second instruction.

14. The apparatus according to claim 10 , wherein the pipelined processor comprises a first-in first-out (FIFO) circuit, and wherein the hardware fence detects if a hazard condition exists by comparing an address for a read operation with an address for a write operation, wherein the read and write operations are stored in the FIFO circuit.

15. A method of processing information in a pipelined processor comprising branched parallel processing paths for instructions, and a hardware fence that maintains increasing transaction identifications (IDs) representing a submitted order on when instructions enter and are being processed within the branched parallel processing paths, the method comprising checking the increasing transaction IDs at a pipeline element level to stall a pipeline element when advancement of a pipeline stage of the branched parallel processing paths would produce an erroneous result.

16. The method according to claim 15 , wherein the increasing transaction IDs can be used to determine when a transaction for a stage representing part of an instruction results in a hazard by comparing an address for an input operation with an address for an output operation, wherein the input operation comprises a read operation, and wherein the output operation comprises a write operation.

17. The method according to claim 16 , wherein determining a hazard condition further comprises determining whether a later read operation has an address specified that matches an address specified for an earlier write operation.

18. The method according to claim 15 , wherein the pipelined processor comprises a first-in first-out (FIFO) circuit, and wherein determining a hazard condition further comprises comparing an address for an input operation with an address for an output operation stored in the FIFO circuit.

19. The method according to claim 15 , wherein increasing transaction IDs are modulo IDs.

20. The method according to claim 15 , further comprising stalling the pipeline processor in response to the hardware fence detecting that a hazard condition exists.

Assignees

• Silicon Lab Inc

Inventors

• Johnson Mark W
• Deal Eric
• Ren Junkang

Classifications

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title