Context-aware bit-stream generator for deterministic stochastic computing

Patent metadata

Field	Value
Publication number	US-12411659-B2
Application number	US-202117343971-A
Country	US
Kind code	B2
Filing date	Jun 10, 2021
Priority date	Jun 10, 2020
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

Disclosed herein are three context-aware architectures to accelerate the three state-of-the-art deterministic methods of SC. The proposed designs employ a control unit to extract the minimum bit-width required to precisely represent each input data. The lengths of bit-streams are reduced to the minimum lengths required to precisely represent each input data. The noise-tolerance property of the designs is preserved as each bit-flip can only introduce a least significant bit error. The proposed designs achieve a considerable improvement in the processing time at a reasonable hardware cost overhead. The proposed designs make the deterministic bit-stream processing more appealing for applications that expect highly accurate computation and also for error-tolerant applications.

First claim

We claim:

1. A method for processing input data in a deterministic bit-stream processing computing system, comprising:
(a) providing two or more context-aware bit-stream generators, comprising:
a modified counter, comprising an n-bit input;
a control unit;
a constant register;
a comparator;
wherein two or more output bits of the modified counter are connected to the comparator in reverse order;
(b) for each context-aware bit-stream generator:
(i) receiving n-bit input data by the constant register;
(ii) the control unit reads the n-bit input data in the constant register;
(iii) the control unit determines a minimum data width for representing the n-bit input data;
(iv) sending the minimum data width determined by the control unit to the modified counter;
(v) sending the two or more output bits of the modified counter to the comparator in reverse order;
(vi) comparing the two or more output bits of the modified counter to the n-bit input data of the constant register; and
(vii) generating a low-discrepancy bit stream;
(c) inputting each low-discrepancy bit stream to a stochastic processing unit;
(d) converting an output of the stochastic processing unit to binary by a stochastic to binary converter.

2. The method of claim 1 , wherein the modified counter further comprises:
two or more JK flip flop gates;
two or more XNOR gates; and
an AND gate;
wherein outputs of the two or more JK flip flop gates provide inputs for the two or more XNOR gates; and wherein outputs of the two or more XNOR gates provide inputs for the AND gate.

3. The method of claim 1 , wherein the control unit comprises:
a stochastic number generator (SNG);
two or more OR gates; and
the constant register.

4. The method of claim 1 , further comprising, for each context-aware bit-stream generator, an output of the modified counter provides an input to the modified counter of a next sequential context-aware bit-stream generator.

5. The method of claim 1 , further comprising sending a stop signal to the stochastic to binary converter by a last in sequence context-aware bit-stream generator.

6. The method of claim 1 , wherein each context-aware bit-stream generator except for a first in sequence context-aware bit-stream generator further comprises an additional modified counter and an AND gate.

7. The method of claim 1 , wherein each context-aware bit-stream generator except for a first in sequence context-aware bit-stream generator further comprises an additional modified counter and an AND gate; and wherein each modified counter provides an inhibit signal to a next sequential context-aware bit-stream generator's modified counter and additional modified counter.

8. A computing architecture for deterministic bit-stream processing, comprising:
two or more binary-to-stochastic converters (BSCs);
wherein each BSC comprises:
an input;
an output;
a clock signal;
a context-aware bit-stream generator, comprising:
a constant register configured to receive n-bit input data;
a control unit configured to read the n-bit input data in the constant register and determine a minimum data width for representing the n-bit input data;
a modified counter configured to receive the minimum data width determined by the control unit;
a comparator configured to receive output bits of the modified counter in reverse order and compare the output bits of the modified counter to the n-bit input data of the constant register to generate a low discrepancy bit stream;

a stop signal;
a stochastic processing unit; and
a stochastic to binary converter;
wherein the output of each BSC provides an input to the stochastic processing unit; and

the output of the stochastic processing unit provides an input to the stochastic to binary converter.

9. The computing architecture of claim 8 , wherein each modified counter provides an input to a next sequential BSC's the modified counter.

10. The computing architecture of claim 8 , wherein each BSC except for a first sequential BSC comprise an additional modified counter.

11. The computing architecture of claim 8 , wherein each BSC except for a first sequential BSC comprise an additional modified counter and an AND gate; and
wherein each modified counter provides an inhibit signal to a next sequential BSC's modified counter and additional modified counter.

12. The computing architecture of claim 8 , wherein each BSC except for a first sequential BSC comprise an additional modified counter and an AND gate; and wherein one input of the AND gate comprises a NOT function.

13. The computing architecture of claim 8 , further comprising a counter that is shared by all BSCs.

Assignees

• Univ Louisiana At Lafayette

Inventors

• Asadi Sina
• Najafi Mohammad Hassan

Classifications

• H03M7/26

  Conversion to or from stochastic codes · CPC title

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G06F7/70 Primary

  using stochastic pulse trains, i.e. randomly occurring pulses the average pulse rates of which represent numbers {(conversion of analogue signals into stochastic pulse trains and vice versa H03M1/04)} · CPC title