Variable resistance memory device

Patent metadata

Field	Value
Publication number	US-12408566-B2
Application number	US-202318338707-A
Country	US
Kind code	B2
Filing date	Jun 21, 2023
Priority date	Dec 27, 2019
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

First claim

What is claimed is:

1. A variable resistance memory device comprising:
a variable resistance layer including a first layer, a second layer, and a third layer,
the second layer on the first layer,
the first layer including a first material,
the second layer including a second material having a valence different from a valence of the first material,
the third layer on the second layer, the third layer including a third material having a valence different from a valence of the second material; and
a first conductive element and a second conductive element on the variable resistance layer and separated from each other so that an electric current path is formed in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

2. The variable resistance memory device of claim 1 , wherein a difference between the valence of the first material and the valence of the second material is 1 or greater.

3. The variable resistance memory device of claim 1 , wherein a difference between a density of the first material and a density of the second material is 1 g/cm 3 or greater.

4. The variable resistance memory device of claim 1 , wherein the first layer and the third layer include a same material.

5. The variable resistance memory device of claim 1 , wherein
the variable resistance layer further includes a fourth layer on the third layer, and
the fourth layer includes a fourth material having a valence that is different from the valence of the third material.

6. The variable resistance memory device of claim 5 , wherein the first material is same as the third material.

7. The variable resistance memory device of claim 5 , wherein the second material is same as the fourth material.

8. The variable resistance memory device of claim 1 , wherein the first material and the second material include oxide materials having a band gap energy of 2 eV or greater.

9. The variable resistance memory device of claim 1 , wherein each of the first material and the second material independently include one of Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO, Nb 2 O 5 , NiO, Ta 2 O 5 , WO 3 , V 2 O 5 , La 2 O 3 , Gd 2 O 3 , CuO, MoO 3 , Cr 2 O 3 , and MnO 2 .

10. A variable resistance memory device comprising:
a support layer including an insulating material;
a variable resistance layer on the support layer, the variable resistance layer including a first layer, and a second layer,
the second layer on the first layer, the first layer including a first material, the second layer including a second material having a valence different from a valence of the first material;
a channel layer on the variable resistance layer;
a gate insulating layer on the channel layer; and
a plurality of gate electrodes on the gate insulating layer, the plurality of gate electrodes being separated from one another, and the plurality of gate electrodes being configured to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

11. The variable resistance memory device of claim 10 , wherein a difference between the valence of the first material and the valence of the second material is 1 or greater.

12. The variable resistance memory device of claim 10 , wherein a difference between a density of the first material and a density of the second material is 1 g/cm 3 or greater.

13. The variable resistance memory device of claim 10 , wherein
each of the first layer and the second layer have a thickness of 10 nm or less, and
the second layer is directly on the first layer.

14. The variable resistance memory device of claim 10 , wherein each of the first material and the second material includes oxide materials having a band gap energy of 2 eV or greater.

15. The variable resistance memory device of claim 10 , wherein each of the first material and the second material independently include one of Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO, Nb 2 O 5 , NiO, Ta 2 O 5 , WO 3 , V 2 O 5 , La 2 O 3 , Gd 2 O 3 , CuO, MoO 3 , Cr 2 O 3 , or MnO 2 .

16. The variable resistance memory device of claim 10 , wherein the variable resistance layer, the channel layer and the gate insulating layer are arranged to form a shape of cylindrical pillar of which vertical direction is parallel to a direction along which the plurality of gate electrodes are spaced apart.

17. A variable resistance memory device comprising:
a variable resistance layer including a first layer and a second layer,
the second layer on the first layer,
the first layer including a first material,
the second layer including a second material having a valence different from a valence of the first material; wherein each of the first layer and, the second layer have a thickness of 10 nm or less; and
a first conductive element and a second conductive element on the variable resistance layer and separated from each other so that an electric current path is formed in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

18. The variable resistance memory device of claim 17 , wherein a difference between the valence of the first material and the valence of the second material is 1 or greater.

19. The variable resistance memory device of claim 17 , wherein a difference between a density of the first material and a density of the second material is 1 g/cm 3 or greater.

20. The variable resistance memory device of claim 17 , wherein each of the first material and the second material independently include one of Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO, Nb 2 O 5 , NiO, Ta 2 O 5 , WO 3 , V 2 O 5 , La 2 O 3 , Gd 2 O 3 , CuO, MoO 3 , Cr 2 O 3 , or MnO 2 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seyun
• Kim Jinhong
• Mizusaki Soichiro
• Yoon Jungho
• Cho Youngjin

Classifications

• H10N70/8833 Primary

  Binary metal oxides, e.g. TaOx · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10N70/883

  Oxides or nitrides · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/8265

  on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices · CPC title