Imaging device and method of manufacturing imaging device
US-2018176490-A1 · Jun 21, 2018 · US
High efficiency microdevice
US12408486B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12408486-B2 |
| Application number | US-202017631005-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 29, 2020 |
| Priority date | Jul 30, 2019 |
| Publication date | Sep 2, 2025 |
| Grant date | Sep 2, 2025 |
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- Title
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Abstract
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A vertical solid state device comprising: a connection pad; and side walls comprising a metal-insulator-semiconductor (MIS) structure; wherein a gate of the MIS structure is shorted to at least one contact of the vertical solid state device and a threshold voltage (VT) of the MIS structure is adjusted to increase the efficiency of the device.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method to increase efficiency in a vertical solid state device, the method comprising: providing a solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure; applying a biasing voltage to a gate electrode connected to the MIS structure and shorting the MIS structure to a n-contact of the vertical solid state device; and keeping the biasing voltage of the gate electrode less than a threshold voltage of the MIS structure to increase the efficiency of the vertical solid state device. 2. The method of claim 1 , wherein a leakage current due to sidewall effect is substantially in a n-contact region of the vertical solid state device. 3. The method of claim 1 , wherein the threshold voltage is adjusted through one of: layer engineering, processing step, or charge implantation. 4. The method of claim 1 , wherein a leakage current due to sidewall effect is entirely in a n-contact region of the vertical solid state device. 5. The method of claim 1 , wherein the gate electrode fully covers the sidewalls of the device.
Assignees
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Classifications
Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title
Multiple bond pads having different shapes · CPC title
Bond pads specially adapted therefor · CPC title
Plan-view shape, i.e. in top view · CPC title
Dispositions of multiple bumps · CPC title
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Frequently asked questions
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- What does patent US12408486B2 cover?
- A vertical solid state device comprising: a connection pad; and side walls comprising a metal-insulator-semiconductor (MIS) structure; wherein a gate of the MIS structure is shorted to at least one contact of the vertical solid state device and a threshold voltage (VT) of the MIS structure is adjusted to increase the efficiency of the device.
- Who is the assignee on this patent?
- Vuereal Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W42/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 02 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).