Solid-state imaging device and imaging apparatus

Patent metadata

Field	Value
Publication number	US-12408454-B2
Application number	US-202218263729-A
Country	US
Kind code	B2
Filing date	Jan 28, 2022
Priority date	Feb 10, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A solid-state imaging device ( 200 ) includes a photoelectric conversion device ( 211 ), a current-voltage conversion circuit ( 310 ), and an output circuit. The photoelectric conversion device ( 211 ) performs photoelectric conversion of incident light. The current-voltage conversion circuit ( 310 ) includes a first transistor ( 311 ) that converts an amount of electric charge generated by photoelectric conversion into a voltage signal. The output circuit includes a second transistor having an S value smaller than an S value of the first transistor ( 311 ) and generates an output signal based on the voltage signal.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
a photoelectric conversion device that performs photoelectric conversion of incident light;
a current-voltage conversion circuit including a first transistor that converts an amount of electric charge generated by the photoelectric conversion into a voltage signal; and
an output circuit that includes a second transistor having an S value smaller than an S value of the first transistor and generates an output signal based on the voltage signal.

2. The solid-state imaging device according to claim 1 , wherein
the second transistor is an amplification transistor included in the output circuit.

3. The solid-state imaging device according to claim 1 , wherein
the output circuit includes a subtractor that calculates a change in the amount of electric charge, and
the subtractor includes the second transistor.

4. The solid-state imaging device according to claim 1 , wherein
the current-voltage conversion circuit further includes a third transistor having an S value smaller than the S value of the first transistor.

5. The solid-state imaging device according to claim 1 , wherein
the second transistor has a gate length longer than a gate length of the first transistor.

6. The solid-state imaging device according to claim 1 , wherein
the first transistor has a channel region on which ion implantation of an impurity having a polarity different from a polarity of the first transistor is performed, and
the second transistor has a channel region on which ion implantation of an impurity having the same polarity as the polarity of the second transistor is performed.

7. The solid-state imaging device according to claim 1 , wherein
the second transistor has an impurity region between a source and a drain shallower than an impurity region of the first transistor, and an impurity distribution of the impurity region of the second transistor is lower than an impurity distribution of the impurity region of the first transistor.

8. The solid-state imaging device according to claim 1 , wherein
the second transistor has a sidewall thicker than a sidewall of the first transistor.

9. The solid-state imaging device according to claim 1 , wherein
a reverse voltage is applied to a body terminal of the second transistor, and a forward voltage is applied to a body terminal of the first transistor.

10. The solid-state imaging device according to claim 1 , wherein
the second transistor has a device region layer having a thickness smaller than a thickness of a device region layer of the first transistor.

11. The solid-state imaging device according to claim 1 , wherein
the first transistor and the second transistor are fin field-effect transistors (FinFET), and
a width of a fin of the second transistor is smaller than a width of a fin of the first transistor.

12. The solid-state imaging device according to claim 1 , wherein
the first and second transistors are transistors having a gate-all-around (GAA) structure, and
a thickness of a channel of the second transistor is smaller than a thickness of a channel of the first transistor.

13. The solid-state imaging device according to claim 1 , wherein
the first transistor is a transistor having a PDSOI substrate structure, and
the second transistor is a transistor having a bulk structure.

14. The solid-state imaging device according to claim 1 , wherein
the first transistor is a transistor having a bulk structure, and
the second transistor is a transistor having a FDSOI substrate structure.

15. The solid-state imaging device according to claim 1 , wherein
the first transistor is a transistor having a bulk structure or a transistor having a PDSOI substrate structure, and
the second transistor is a fin field-effect transistor in which a width of a fin is smaller than ⅓ of a gate length.

16. The solid-state imaging device according to claim 1 , wherein
the first transistor and the second transistor are disposed on different substrates.

17. The solid-state imaging device according to claim 1 , wherein
the output circuit outputs a luminance change of the incident light incident on the photoelectric conversion device as the output signal based on the voltage signal.

18. An imaging apparatus comprising:
a solid-state imaging device; and
a processor that processes an output signal output from the solid-state imaging device, wherein
the solid-state imaging device includes:
a photoelectric conversion device that performs photoelectric conversion of incident light;
a current-voltage conversion circuit including a first transistor that converts an amount of electric charge generated by the photoelectric conversion into a voltage signal; and
an output circuit that includes a second transistor having an S value smaller than an S value of the first transistor and generates an output signal based on the voltage signal.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Hanzawa Katsuhiko
• Miyake Shinichi
• Tomida Kazuyuki

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• H10D30/021

  of FETs having insulated gates [IGFET] · CPC title

• H04N25/47

  Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data · CPC title

• H10F39/80373

  characterised by the gate of the transistor · CPC title