Identifying and marking failed egress links in data plane

Patent metadata

Field	Value
Publication number	US-12407564-B2
Application number	US-202318495590-A
Country	US
Kind code	B2
Filing date	Oct 26, 2023
Priority date	Feb 8, 2016
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.

First claim

What is claimed is:

1. An integrated circuit for use in association with a network switch in packet forwarding-related operations in a network, the integrated circuit comprising:
programmable packet data processing pipeline hardware for use in (1) parsing and identifying header field data of received packet data and (2) matching the header field data to programmable match-action table data to determine one or more packet processing-related actions that correspond to the header field data, the one or more packet processing-related actions to be carried out in processing of the packet data, the programmable packet data processing pipeline hardware comprising ingress pipeline hardware and egress pipeline hardware; and
shared buffer memory to be shared between the ingress pipeline hardware and the egress pipeline hardware for use in (1) storing at least one portion of the received packet data sent from the ingress pipeline hardware and (2) providing the at least one portion of the received packet data stored in the shared buffer memory to the egress pipeline hardware;
wherein: the ingress pipeline hardware and the egress pipeline hardware are configurable to comprise respective pluralities of pipelines;
when the integrated circuit is in operation:
the parsing, the identifying, and the programmable match-action table data are programmable based upon software-generated configuration data to be provided to the integrated circuit;
in event of failure of at least one path for packet data transmission, the integrated circuit is configurable to select, based upon at least one data structure maintained at a data plane of the integrated circuit, at least one alternative path for the packet data transmission, the at least one path and/or the at least one alternative path being configurable to correspond to multiple respective network hops from the network switch, wherein the at least one alternative path is for use in association with multi-path transmission;
the at least one data structure is configurable to indicate primary and alternative tunnel-related transmission paths for use in the packet data transmission; the integrated circuit is to implement the one or more packet processing-related actions;
the one or more packet processing-related actions are configurable to comprise:
one or more equal-cost multi-path routing operations;

the integrated circuit is configurable to generate flow-related information and statistics-related information usable in association with software-defined networking;
the flow-related information is configurable to comprise data flow rate information; and
the statistics-related information is configurable to comprise packet count information and/or byte count information.

2. The integrated circuit of claim 1 , wherein:
the integrated circuit comprises ternary content addressable memory to store the programmable match-action table data.

3. The integrated circuit of claim 2 , wherein:
the primary and the alternative tunnel-related transmission paths are associated with respective ports and/or respective links that are associated with the integrated circuit.

4. The integrated circuit of claim 3 , wherein:
the integrated circuit comprises an application specific integrated circuit (ASIC) that is for use in association with another integrated circuit.

5. At least one non-transitory machine-readable storage medium storing instructions for being executed by an integrated circuit, the integrated circuit to be used in association with a network switch in packet forwarding-related operations in a network, the integrated circuit comprising programmable packet data processing pipeline hardware and shared buffer memory, the programmable packet data processing pipeline hardware comprising ingress pipeline hardware and egress pipeline hardware, the shared buffer memory to be shared between the ingress pipeline hardware and the egress pipeline hardware, the instructions, when executed by the integrated circuit, resulting in the integrated circuit being configured for performance of operations comprising:
parsing and identifying, by the programmable packet data processing pipeline hardware, header field data of received packet data;
matching, by the programmable packet data processing pipeline hardware, the header field data to programmable match-action table data to determine one or more packet processing-related actions that correspond to the header field data, the one or more packet processing-related actions to be carried out in processing of the packet data;
storing, in the shared buffer memory, at least one portion of the received packet data sent from the ingress pipeline hardware; and
providing the at least one portion of the received packet data stored in the shared buffer memory to the egress pipeline hardware;
wherein:
the ingress pipeline hardware and the egress pipeline hardware are configurable to comprise respective pluralities of pipelines;
when the integrated circuit is in operation:
the parsing, the identifying, and the programmable match-action table data are programmable based upon software-generated configuration data to be provided to the integrated circuit;
in event of failure of at least one path for packet data transmission, the integrated circuit is configurable to select, based upon at least one data structure maintained at a data plane of the integrated circuit, at least one alternative path for the packet data transmission, the at least one path and/or the at least one alternative path being configurable to correspond to multiple respective network hops from the network switch, wherein the at least one alternative path is for use in association with multi-path transmission;
the at least one data structure is configurable to indicate primary and alternative tunnel-related transmission paths for use in the packet data transmission;
the integrated circuit is to implement the one or more packet processing-related actions;
the one or more packet processing-related actions are configurable to comprise:
one or more equal-cost multi-path routing operations;
the integrated circuit is configurable to generate flow-related information and statistics-related information usable in association with software-defined networking;
the flow-related information is configurable to comprise data flow rate information; and
the statistics-related information is configurable to comprise packet count information and/or byte count information.

6. The at least one non-transitory machine-readable storage medium of claim 5 , wherein:
the integrated circuit comprises ternary content addressable memory to store the programmable match-action table data.

7. The at least one non-transitory machine-readable storage medium of claim 6 , wherein:
the primary and the alternative tunnel-related transmission paths are associated with respective ports and/or respective links that are associated with the integrated circuit.

8. The at least one non-transitory machine-readable storage medium of claim 7 , wherein:
the integrated circuit comprises an application specific integrated circuit (ASIC) that is for use in association with another integrated circuit.

9. A method implemented using an integrated circuit, the integrated circuit to be used in association with a network switch in packet forwarding-related operations in a network, the integrated circuit comprising programmable packet data processing pipeline hardware and shared buffer memory, the programmable packet data processing pipeline hardware comprising ingress pipeline hardware and egress pipeline hardware, the shared buffer memory to be shared between the ingress pipeline hardware and the egress pipeline hardware, the method comprising:
parsing and ide

Assignees

• Barefoot Networks Inc

Inventors

• Kodeboyina Chaitanya
• Cruz John
• Licking Steven
• Attig Michael E

Classifications

• H04L45/64

  using an overlay routing layer · CPC title

• H04L45/28

  using route fault recovery · CPC title

• H04L49/555

  Error detection · CPC title

• H04L45/42

  Centralised routing · CPC title

• H04L49/3063

  Pipelined operation · CPC title