Frequency multiplier

Patent metadata

Field	Value
Publication number	US-12407298-B2
Application number	US-202218571089-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Jun 17, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A frequency multiplier is provided. A harmonic generator of the frequency multiplier comprises: a harmonic generating core unit; a first resonant tank which is connected to a first output terminal and a second output terminal of the harmonic generating core unit; and a first feedback circuit which is connected to the first output terminal and the second output terminal of the harmonic generating core unit to change the effective resistance of the first resonant tank.

First claim

What is claimed is:

1. A frequency multiplier comprising:
a harmonic generator,
wherein the harmonic generator includes:
a harmonic generating core unit;
a first resonant tank connected to a first output terminal and a second output terminal of the harmonic generating core unit; and
a first feedback circuit connected to the first output terminal and the second output terminal of the harmonic generating core unit to change effective resistance of the first resonant tank,
wherein the first feedback circuit includes an oscillation control loop configured to control an output voltage between the first output terminal and the second output terminal to converge to a predetermined reference voltage,
wherein the first feedback circuit is configured to generate an effect of adding negative parallel resistance to parasitic resistance of the first resonant tank,
wherein the first feedback circuit is configured to increase an effective resistance value of the resonant tank to be greater than a parasitic resistance value of the first resonant tank,
wherein the harmonic generating core unit includes:
a first transistor;
a second transistor;
a third transistor and a fourth transistor forming a first differential pair; and
a fifth transistor and a sixth transistor forming a second differential pair,

wherein the third transistor and the fifth transistor are connected to the first output terminal, and the fourth transistor and the sixth transistor are connected to the second output terminal,
wherein the first feedback circuit includes:
a seventh transistor; and
an eighth transistor and a ninth transistor that are connected to the seventh transistor and cross-coupled to each other, and

wherein the oscillation control loop includes a detector configured to measure a voltage between the first output terminal and the second output terminal, a non-inverting amplifier connected to the detector, and an operational amplifier connected to the non-inverting amplifier and of which an output terminal is connected to the seventh transistor.

2. The frequency multiplier of claim 1 , wherein a non-inverting terminal of the non-inverting amplifier is connected to an output terminal of the detector,
the reference voltage is applied to an inverting terminal of the non-inverting amplifier, and
an output terminal of the non-inverting amplifier is connected to an inverting terminal of the operational amplifier.

3. The frequency multiplier of claim 1 , wherein the oscillation control loop includes an eleventh transistor, a twelfth transistor connected to a gate of the eleventh transistor and connected to the eighth transistor and the ninth transistor, and a thirteenth transistor connected to a non-inverting terminal of the operational amplifier.

4. A frequency multiplier comprising:
a harmonic generator; and
a cascode buffer connected to the harmonic generator,
wherein the harmonic generator includes:
a harmonic generating core unit;
a first resonant tank connected to a first output terminal and a second output terminal of the harmonic generating core unit; and
a first feedback circuit connected to the first output terminal and the second output terminal of the harmonic generating core unit to change effective resistance of the first resonant tank,
wherein the cascode buffer includes:
a buffer core unit;
a second resonant tank connected to a first output terminal and a second output terminal of the buffer core unit; and
a second feedback circuit connected to the first output terminal and the second output terminal of the buffer core unit to generate an effect of adding negative parallel resistance to parasitic resistance of the resonant tank,
wherein the buffer core unit includes a first transistor and a third transistor connected in a cascode structure and a second transistor and a fourth transistor connected in a cascode structure,
wherein the second feedback circuit includes:
a fifth transistor; and
a sixth transistor and a seventh transistor that are connected to the fifth transistor and cross-coupled to each other,
wherein the second feedback circuit includes an oscillation control loop configured to control an output voltage between the first output terminal and the second output terminal to converge to a predetermined reference voltage.

5. The frequency multiplier of claim 4 , wherein the oscillation control loop includes a detector configured to measure a voltage between the first output terminal and the second output terminal, a non-inverting amplifier connected to the detector, and an operational amplifier connected to the non-inverting amplifier and of which an output terminal is connected to the fifth transistor.

Assignees

• Univ Kookmin Ind Acad Coop Found

Inventors

• Park Jun Seok
• Hong Nam Pyo
• Nam kyu hyun

Classifications

• H03B19/14 Primary

  by means of a semiconductor device · CPC title

• H03B2200/0074

  Locking of an oscillator by injecting an input signal directly into the oscillator · CPC title

• H03B5/1265

  switched capacitors · CPC title

• H03L7/24

  using a reference signal directly applied to the generator · CPC title

• H03B5/1228

  the amplifier comprising one or more field effect transistors · CPC title