Semiconductor device package

Patent metadata

Field	Value
Publication number	US-12406935-B2
Application number	US-202418405806-A
Country	US
Kind code	B2
Filing date	Jan 5, 2024
Priority date	Apr 5, 2018
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A semiconductor device package includes a substrate; and a plurality of semiconductor structures disposed to be spaced apart from each other at a central portion of the substrate. Further, the semiconductor structure is disposed on the substrate and includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer disposed on the first conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. The semiconductor device package also includes a plurality of first interconnection lines disposed between the substrate and the plurality of semiconductor structures and electrically connected to the first conductivity-type semiconductor layer; and a plurality of second interconnection lines disposed between the substrate and the plurality of semiconductor structures and electrically connected to the second conductivity-type semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device package comprising:
a substrate;
a plurality of semiconductor structures disposed to be spaced apart from each other at a central portion of the substrate,
wherein the semiconductor structure is disposed on the substrate and comprises a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer disposed on the first conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer;
a first recess formed to pass through the second conductivity-type semiconductor layer, the active layer and extends to a partial region of the first conductivity-type semiconductor layer;
a first electrode disposed on the first conductivity-type semiconductor layer and electrically connected to the first conductivity-type semiconductor layer;
a second electrode disposed below the second conductivity-type semiconductor layer and electrically connected to the second conductivity-type semiconductor layer;
a plurality of first interconnection lines disposed between the substrate and the plurality of semiconductor structures and electrically connected to the first conductivity-type semiconductor layer through the first electrode;
a plurality of second interconnection lines disposed between the substrate and the plurality of semiconductor structures and electrically connected to the second conductivity-type semiconductor layer through the second electrode; and
a reflective layer disposed between the second electrode and the second interconnection line,
wherein the first electrode is disposed in the first recess.

2. The semiconductor device package of claim 1 , further comprising:
a passivation layer disposed on the semiconductor structure and comprising a plurality of layers; and
an intermediate layer disposed inside the passivation layer.

3. The semiconductor device package of claim 2 , wherein the passivation layer is disposed on an outermost surface of the first conductivity-type semiconductor layer and a portion of an upper surface of the first conductivity-type semiconductor layer.

4. The semiconductor device package of claim 3 , wherein the plurality of layers comprise:
a first passivation layer disposed to be in contact with the outermost surface and the portion of the upper surface of the first conductivity-type semiconductor layer;
a second passivation layer disposed on the first passivation layer,
wherein the intermediate layer is disposed between the first passivation layer and the second passivation layer.

5. The semiconductor device package of claim 2 , wherein the intermediate layer extends from an outermost surface of the first conductivity-type semiconductor layer to an edge of the substrate.

6. The semiconductor device package of claim 2 , wherein the intermediate layer comprises a plurality of layers and is made of any one selected from among metal, ceramic, and semiconductor materials.

7. The semiconductor device package of claim 2 , wherein a ratio of a thickness of the intermediate layer to a maximum height of an outermost surface of the first conductivity-type semiconductor layer on a lower surface of the first conductivity-type semiconductor layer is in a range of 1:11.25 to 1:30.

8. The semiconductor device package of claim 2 , further comprising:
a fluorescent layer disposed on the plurality of semiconductor structures and the passivation layer.

9. The semiconductor device package of claim 8 , wherein a ratio of a maximum height of an outermost surface of the first conductivity-type semiconductor layer to a thickness of the fluorescent layer is in a range of 1:1.1 to 1:2.3.

10. The semiconductor device package of claim 1 , further comprising:
a first insulating layer disposed between the first interconnection line and the second interconnection line;
a plurality of first pads electrically connected to the first interconnection lines; and
a plurality of second pads electrically connected to the second interconnection lines,
wherein the semiconductor structure is disposed between the first pad and the second pad.

11. The semiconductor device package of claim 10 , wherein
the first interconnection line comprises a first through-portion, which passes through the active layer, the second conductivity-type semiconductor layer and the first insulating layer, and is electrically connected to the first electrode, a first end portion, which extends to an edge of the substrate and is electrically connected to the first pad, and a first connection portion, which disposed between the first through-portion and the end portion, and the second interconnection line comprises a second end portion that extends to the edge of the substrate and is electrically to the second pad.

12. The semiconductor device package of claim 1 , wherein an upper surface of the first conductivity-type semiconductor layer comprises a first surface, a second surface disposed below the first surface, and an inclined surface positioned between the first surface and the second surface.

13. The semiconductor device package of claim 12 , wherein a ratio of a height from a lower surface of the first conductivity-type semiconductor layer to the second surface to a height from the lower surface exposed by the first recess to the first surface is in a range of 1:1 to 1:10.

14. The semiconductor device package of claim 12 , wherein a length of the second surface in a direction perpendicular to a thickness direction of the semiconductor structure is in a range of 10 μm to 150 μm.

15. The semiconductor device package of claim 1 , wherein a maximum height of an outermost surface of the first conductivity-type semiconductor layer is in a range of 1 μm to 3 μm.

16. The semiconductor device package of claim 1 , wherein a length ratio of a minimum separation distance between adjacent semiconductor structures to a maximum width of the semiconductor structure is in a range of 1:5 to 1:20.

17. The semiconductor device package of claim 1 , wherein an upper surface of the first conductivity-type semiconductor layer is formed with an uneven structure.

Assignees

• Suzhou Lekin Semiconductor Co Ltd

Inventors

• Lee Sang Youl
• Kang Ki Man
• Lee Eun Dk

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title