Method of managing memory in an integrated circuit card and corresponding integrated circuit card

Patent metadata

Field	Value
Publication number	US-12406707-B2
Application number	US-202318295558-A
Country	US
Kind code	B2
Filing date	Apr 4, 2023
Priority date	Apr 15, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A method of managing memory in an integrated circuit card comprising a non-volatile memory portion and a RAM memory portion, the method comprising creating in a non-volatile memory heap one or more array pointers, corresponding to one or more transient arrays to be allocated, each array pointer comprising a transient array size and a transient array address, wherein the creating comprises creating one or more array pointers comprising as transient array address a logical address of the area of the RAM memory portion in which the respective transient array is to be allocated, and assigning then in the RAM memory area memory only to transient arrays, corresponding to the respective one or more array pointers, which comprise at least a value different from zero.

First claim

What is claimed is:

1. A method of managing memory in an integrated circuit card having a non-volatile memory portion and a random access memory (RAM) memory portion, the method comprising:
creating, in a non-volatile memory heap in the non-volatile memory portion, one or more array pointers corresponding to respective one or more transient arrays to be allocated in the RAM memory portion, each array pointer comprising a transient array size and a transient array address, each transient array address being a logical or indirect address pointing indirectly to an area of the RAM memory portion in which a respective transient array is to be allocated; and
assigning, in the RAM memory portion, memory only to non-zero transient arrays having at least one value different from zero.

2. The method according to claim 1 , wherein:
the creating the one or more array pointers comprises creating the one or more array pointers with a required body size and writing a null value in each transient array address as a body logical address; and
the assigning comprises, based on writing a value different from zero in any point of an array body, assigning a memory area of the RAM memory portion, with the required body size, to the corresponding transient array, and saving the corresponding transient array address in the body logical address of the corresponding array pointer.

3. The method according to claim 1 , further comprising providing an indirection table, stored in the RAM memory portion, comprising reference addresses pointing to physical locations of respective arrays in the RAM memory portion, and to which the RAM array pointers in the non-volatile memory portion ordinately point.

4. The method according to claim 3 , wherein each RAM array pointer comprises as the respective transient array address an indirect address that comprises a null value or an address of the memory area containing the indirection table in the RAM memory portion, comprising a corresponding reference address that contains a physical address of the RAM memory portion assigned to the respective transient array.

5. The method according to claim 1 , further comprising deallocating, in the RAM memory portion, each transient array having values all equal to zero.

6. The method according to claim 2 , further comprising storing in the logical or indirect address either an address of the memory area assigned to the array body or the null value.

7. The method according to claim 5 , wherein the deallocating comprises, based on each transient array in the RAM memory portion being filled with zeroes, writing in the logical or indirect address of the corresponding array pointer a zero value.

8. The method according to claim 1 , further comprising performing a Java Card method for making the transient arrays.

9. The method according to claim 1 , further comprising:
applying a checking rule checking whether a memory value representing a sum of a size of all the created transient arrays is greater than a memory value representing a total physical memory in the RAM memory portion increased by a safety amount that is a function of a settable parameter value; and
signaling an out of memory event in response to the checking rule being affirmative.

10. The method according to claim 9 , wherein the function is multiplying or summing by the settable parameter value.

11. The method according to claim 9 , further comprising:
performing the checking in response to an application selection; and
in response to the out of memory event, requesting a failure of the application selection.

12. An integrated circuit card, comprising:
a non-volatile memory portion;
a random access memory (RAM) memory portion; and
a processor communicatively coupled to the non-volatile memory portion and the RAM memory portion, and configured to:
create, in a non-volatile memory heap in the non-volatile memory portion, one or more array pointers corresponding to respective one or more transient arrays to be allocated in the RAM memory portion, each array pointer comprising a transient array size and a transient array address, each transient array address being a logical or indirect address pointing indirectly to an area of the RAM memory portion in which a respective transient array is to be allocated; and
assign, in the RAM memory portion, memory only to non-zero transient arrays having at least one value different from zero.

13. The integrated circuit card according to claim 12 , wherein the integrated circuit card is an embedded Universal Integrated Circuit Card (eUICC) using a Java Card platform.

14. The integrated circuit card according to claim 12 , wherein:
the processor configured to create the one or more array pointers comprises the processor configured to create the one or more array pointers with a required body size and writing a null value in each transient array address as a body logical address; and
the processor configured to assign comprises the processor configured to, based on writing a value different from zero in any point of an array body, assign a memory area of the RAM memory portion, with the required body size, to the corresponding transient array, and save the corresponding transient array address in the body logical address of the corresponding array pointer.

15. The integrated circuit card according to claim 12 , further comprising the processor configured to provide an indirection table, stored in the RAM memory portion, comprising reference addresses pointing to physical locations of respective arrays in the RAM memory portion, and to which the RAM array pointers in the non-volatile memory portion ordinately point.

16. The integrated circuit card according to claim 15 , wherein each RAM array pointer comprises as the respective transient array address an indirect address that comprises a null value or an address of the memory area containing the indirection table in the RAM memory portion, comprising a corresponding reference address that contains a physical address of the RAM memory portion assigned to the respective transient array.

17. The integrated circuit card according to claim 12 , further comprising the processor configured to deallocate, in the RAM memory portion, each transient array having values all equal to zero.

18. The integrated circuit card according to claim 14 , further comprising the processor configured to store in the logical or indirect address either an address of the memory area assigned to the array body or the null value.

19. The integrated circuit card according to claim 12 , further comprising the processor configured to perform a Java Card method for making the transient arrays.

20. The integrated circuit card according to claim 12 , further comprising the processor configured to:
apply a checking rule checking whether a memory value representing a sum of a size of all the created transient arrays is greater than a memory value representing a total physical memory in the RAM memory portion increased by a safety amount that is a function of a settable parameter value; and
signal an out of memory event in response to the checking rule being affirmative.

Assignees

• St Microelectronics Srl

Inventors

• Veneroso Amedeo
• Cimino Carlo

Classifications

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F2212/177

  Smart card · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title