Timing sequence control circuit, timing sequence control method, and semiconductor memory

Patent metadata

Field	Value
Publication number	US-12406706-B2
Application number	US-202318169159-A
Country	US
Kind code	B2
Filing date	Feb 14, 2023
Priority date	May 24, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.

First claim

What is claimed is:

1. A circuit for controlling a timing sequence, comprising a signal transmission module and a timing sequence compensation module, wherein the timing sequence compensation module is connected with the signal transmission module,
wherein the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal,
wherein the timing sequence compensation module at least comprises a compensation capacitor, the timing sequence compensation module is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that a time difference between the sampling signal and a to-be-sampled data (DQ) signal meets a preset requirement;
wherein the timing sequence control circuit further comprises a stabilized voltage supply and a control module, the control module is connected with the stabilized voltage supply,
wherein the control module is configured to detect a parameter change in the timing sequence control circuit, and control the stabilized voltage supply to generate the supply voltage corresponding to the parameter change according to the parameter change and a preset supply voltage generation strategy;
wherein the timing sequence control circuit further comprises a comparison module, the comparison module is connected with the control module,
wherein the comparison module is configured to perform a rising edge comparison between the sampling signal and the to-be-sampled DQ signal, and determine a rising edge time difference value of the sampling signal and the to-be-sampled DQ signal within a same clock cycle,
wherein the control module is further configured to acquire the rising edge time difference value output by the comparison module, and generate the supply voltage corresponding to the rising edge time difference value according to the rising edge time difference value and the preset supply voltage generation strategy.

2. The circuit of claim 1 , wherein the timing sequence control circuit further comprises a clock input circuit and a data input circuit, an input end of the signal transmission module is connected with the clock input circuit, and an output end of the signal transmission module is connected with the data input circuit,
wherein the signal transmission module comprises at least one internal circuit, when there are a plurality of internal circuits, the plurality of internal circuits are connected in sequence in a transmission direction from the clock input circuit to the data input circuit.

3. The circuit of claim 2 , wherein there is at least one timing sequence compensation module, different timing sequence compensation modules correspond to different internal circuits, and each timing sequence compensation module is connected with an output end of a corresponding internal circuit to perform timing sequence compensation on an output signal of the internal circuit.

4. The circuit of claim 2 , wherein the timing sequence control circuit further comprises a power supply module, one end of the compensation capacitor is connected with the power supply module, and another end of the compensation capacitor is connected with an output end of a corresponding internal circuit,
wherein the power supply module is configured to provide and adjust the supply voltage, so as to adjust a discharge speed of the compensation capacitor through coupling effect.

5. The circuit of claim 4 , wherein the timing sequence compensation module further comprises a first switching transistor, a gate electrode of the first switching transistor is connected with the power supply module, a source electrode of the first switching transistor is connected with one end of the compensation capacitor, another end of the compensation capacitor is connected with a low level, and a drain electrode of the first switching transistor being connected with the output end of the corresponding internal circuit,
wherein the power supply module is configured to provide and adjust the supply voltage so as to control the conduction degree of the first switching transistor, and adjust the discharge speed of the compensation capacitor according to the conduction degree of the first switching transistor.

6. The circuit of claim 4 , wherein the compensation capacitor is configured to adjust a delay time of the initial sampling signal,
wherein when an initial delay time of the initial sampling signal by the timing sequence control circuit is increased, a discharge speed of the compensation capacitor is reduced so as to reduce a delay time of the initial sampling signal by the compensation capacitor,
wherein when the initial delay time of the initial sampling signal by the timing sequence control circuit is reduced, the discharge speed of the compensation capacitor is increased so as to increase the delay time of the initial sampling signal by the compensation capacitor.

7. The circuit of claim 2 , wherein the internal circuit comprises a buffer.

8. The circuit of claim 1 , wherein the parameter change in the timing sequence control circuit is a temperature change in the timing sequence control circuit, and the preset supply voltage generation strategy is that a temperature is negatively correlated with the supply voltage within a preset temperature range.

9. The circuit of claim 1 , wherein the parameter change in the timing sequence control circuit is a voltage change of an internal circuit, which is not connected with the timing sequence compensation module, in the timing sequence control circuit, and the preset supply voltage generation strategy is that a voltage of the internal circuit not connected with the timing sequence compensation module is positively correlated with the supply voltage.

10. The circuit of claim 1 , wherein the supply voltage is provided by an internal working power supply or a charge pump, and the charge pump is configured to generate an internal working power supply based on an external power supply.

11. The circuit of claim 1 , wherein the timing sequence control circuit is configured to adjust a timing sequence relationship between the initial sampling signal and the DQ signal,
wherein the initial sampling signal input by the signal transmission module is one of the following: a data strobe (DQS) signal and a write clock (WCK) signal.

12. A semiconductor memory, comprising a circuit for controlling a timing sequence,
wherein the circuit for controlling the timing sequence comprises a signal transmission module and a timing sequence compensation module, wherein the timing sequence compensation module is connected with the signal transmission module,
wherein the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal,
wherein the timing sequence compensation module at least comprises a compensation capacitor, the timing sequence compensation module is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that a time difference between the sampling signal and a to-be-sampled data (DQ) signal meets a preset requirement;
wherein the timing sequence control circuit further comprises a stabilized voltage supply and a control module, the control module is connected with the stabilized voltage supply,
wherein the control module is configured to detect a parameter change in the timing sequence control circuit, and control the stabilized voltage

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling

Classifications

• G11C7/1066

  Output synchronization · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/225

  Clock input buffers · CPC title