Pixel driving circuit and driving method thereof, display panel, and display apparatus

Patent metadata

Field	Value
Publication number	US-12406622-B2
Application number	US-202218263043-A
Country	US
Kind code	B2
Filing date	Jul 21, 2022
Priority date	Jul 21, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A pixel driving circuit includes a driving sub-circuit and a control sub-circuit. The driving sub-circuit is coupled to a data signal terminal, a scan signal terminal, a first power supply voltage terminal, an enable signal control terminal and an element to be driven, and the driving sub-circuit is configured to, in response to an enable signal, transmit a generated driving signal to the element to be driven, and control a current path transmitting the driving signal to be turned on and off. The control sub-circuit is coupled to the enable signal control terminal, and the control sub-circuit is configured to, in response to a signal received at the control signal terminal, transmit a signal received at a first enable signal terminal or a signal received at a second enable signal terminal to the enable signal control terminal.

First claim

What is claimed is:

1. A pixel driving circuit, comprising:
a driving sub-circuit coupled to a data signal terminal, a scan signal terminal, a first power supply voltage terminal, an enable signal control terminal and an element to be driven, the driving sub-circuit being configured to, in response to a signal received at the scan signal terminal, write a data signal received at the data signal terminal into the driving sub-circuit; and the driving sub-circuit being further configured to, generate a driving signal according to the written data signal and a first voltage signal received at the first power supply voltage terminal, and in response to an enable signal received at the enable signal control terminal, transmit the driving signal to the element to be driven, and control a current path transmitting the driving signal to be turned on and off; and
a control sub-circuit coupled to a control signal terminal, a first enable signal terminal, a second enable signal terminal and the enable signal control terminal, the control sub-circuit being configured to, in response to a signal received at the control signal terminal, transmit a signal received at the first enable signal terminal to the enable signal control terminal, or transmit a signal received at the second enable signal terminal to the enable signal control terminal;
wherein the driving sub-circuit includes a data writing sub-circuit and a driving signal generating sub-circuit, wherein
the data writing sub-circuit is coupled to the data signal terminal, the scan signal terminal and a second node, and the data writing sub-circuit is configured to, in response to a scan signal received at the scan signal terminal, transmit the data signal received at the data signal terminal to the second node;
the driving signal generating sub-circuit is coupled to the second node, the first power supply voltage terminal, the enable signal control terminal and the element to be driven, and the driving signal generating sub-circuit is configured to, in response to the enable signal received at the enable signal control terminal and a voltage at the second node, generate the driving signal according to the first voltage signal received at the first power supply voltage terminal; and the driving signal generating sub-circuit is further configured to, in response to the enable signal received at the enable signal control terminal, control a current path through which the driving signal is transmitted to the element to be driven to be turned on and off.

2. The pixel driving circuit according to claim 1 , wherein the driving signal generating sub-circuit includes a driving transistor and an enable transistor;
a first electrode of the driving transistor is coupled to the first power supply voltage terminal, a second electrode of the driving transistor is coupled to a first node, and a control electrode of the driving transistor is coupled to the second node;
a first electrode of the enable transistor is coupled to the first node, a second electrode of the enable transistor is coupled to a third node, and a control electrode of the enable transistor is coupled to the enable signal control terminal; and
the third node is further coupled to a first electrode of the element to be driven, and a second electrode of the element to be driven is coupled to a second power supply voltage terminal.

3. The pixel driving circuit according to claim 1 , wherein the data writing sub-circuit includes: a writing transistor, a first capacitor and a first reset transistor;
a first electrode of the writing transistor is coupled to the data signal terminal, a second electrode of the writing transistor is coupled to the second node, and a control electrode of the writing transistor is coupled to the scan signal terminal;
a first electrode of the first reset transistor is coupled to a first node, a second electrode of the first reset transistor is coupled to a reset signal terminal, and a control electrode of the first reset transistor is coupled to the scan signal terminal; and
a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node.

4. The pixel driving circuit according to claim 1 , wherein the data writing sub-circuit includes: a first transmission transistor, a second transmission transistor and a first capacitor, and the scan signal terminal includes a first scan signal terminal and a second scan signal terminal;
a first electrode of the first transmission transistor is coupled to the data signal terminal, a second electrode of the first transmission transistor is coupled to the second node, and a control electrode of the first transmission transistor is coupled to the first scan signal terminal;
a first electrode of the second transmission transistor is coupled to the data signal terminal, a second electrode of the second transmission transistor is coupled to the second node, and a control electrode of the second transmission transistor is coupled to the second scan signal terminal; and
a first electrode of the first capacitor is coupled to the second node, and a second electrode of the first capacitor is coupled to a reference voltage terminal.

5. The pixel driving circuit according to claim 1 , wherein the pixel driving circuit further comprises a reset sub-circuit coupled to a third node, the scan signal terminal and a reset signal terminal; and the reset sub-circuit is configured to, in response to the scan signal received at the scan signal terminal, transmit a reset signal received at the reset signal terminal to the third node; or
the pixel driving circuit further comprises the reset sub-circuit coupled to the third node, the scan signal terminal and the reset signal terminal; the reset sub-circuit is configured to, in response to the scan signal received at the scan signal terminal, transmit the reset signal received at the reset signal terminal to the third node; and the reset sub-circuit includes a second reset transistor; a first electrode of the second reset transistor is coupled to the third node, a second electrode of the second reset transistor is coupled to the reset signal terminal, and a control electrode of the second reset transistor is coupled to the scan signal terminal.

6. The pixel driving circuit according to claim 1 , wherein the control sub-circuit includes a first enable sub-circuit and a second enable sub-circuit,
the first enable sub-circuit is coupled to a fourth node, the first enable signal terminal and the enable signal control terminal, and the first enable sub-circuit is configured to, in response to a first control signal received at the fourth node, transmit a first enable signal received at the first enable signal terminal to the enable signal control terminal; and
the second enable sub-circuit is coupled to a fifth node, the second enable signal terminal and the enable signal control terminal, and the second enable sub-circuit is configured to, in response to a second control signal received at the fifth node, transmit a second enable signal received at the second enable signal terminal to the enable signal control terminal.

7. The pixel driving circuit according to claim 6 , wherein the first enable sub-circuit includes a first control transistor; a first electrode of the first control transistor is coupled to the first enable signal terminal, a second electrode of the first control transistor is coupled to the enable signal control terminal, and a control electrode of the first control transistor is coupled to the fourth node; and
the second enable sub-circuit includes a second control transistor; a first electrode of the second control transistor is coupled to the second enable signal terminal, a second electrode of the s

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Cong Ning
• Xiao Li
• Zheng Haoliang
• Zhang Can
• Xuan Minghua
• Chen Xiaochuan
• Wang Can
• Niu Jinfei
• Zhang Jingjing

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/062

  Waveforms for resetting a plurality of scan lines at a time · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title