Display substrate, repair method and display device

Patent metadata

Field	Value
Publication number	US-12406604-B2
Application number	US-202218264331-A
Country	US
Kind code	B2
Filing date	Sep 23, 2022
Priority date	Sep 23, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n−m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

First claim

What is claimed is:

1. A display substrate, comprising a base substrate and a driving module arranged on the base substrate; wherein the driving module includes N driving circuits connected in series;
the driving circuit includes an input terminal; N is a positive integer;
input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer;
an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n−m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n;
the driving module further includes at least one connection line, and the connection line extends along a first direction;
there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate;
there is an overlapping portion between the orthographic projection of the connection line on the base substrate and an orthographic projection of the input cascade line on the base substrate,
wherein the driving module includes a plurality of clock signal lines, a plurality of stages of driving circuits and a line collection portion; the driving circuit includes a first driving circuit portion and a second driving circuit portion;
the plurality of clock signal lines, the first driving circuit portion, the line collection portion and the second driving circuit portion are arranged in sequence along a direction close to a display area; the input cascade line is arranged in the line collection portion; the driving circuit includes the first driving circuit portion and the second driving circuit portion, and
wherein the second driving circuit portion includes an output transistor in the driving circuit; the first driving circuit portion includes a pull-up node control sub-circuit, a pull-down node control sub-circuit and an output reset sub-circuit; the pull-up node control sub-circuit is configured to control a potential of the pull-up node, and the pull-down node control sub-circuit is configured to control a potential of the pull-down node, and the output reset sub-circuit is used to reset a driving signal under the control of the potential of the pull-down node.

2. The display substrate according to claim 1 , wherein at least part of the connection line is located on different layers from the initial voltage line, and at least part of the connection line is located on different layers from the input cascade line.

3. The display substrate according to claim 1 , wherein the connection line is arranged between two adjacent driving circuits; or, the connection line penetrates through at least part of the driving circuit.

4. The display substrate according to claim 1 , wherein, the connection line included in the driving module penetrates through the clock signal line, the first driving circuit portion and the line collection portion included in the driving circuit along a direction from away from the display area to close to the display area.

5. The display substrate according to claim 1 , wherein the display panel includes a first metal layer and an electrode layer arranged in sequence in a direction away from the base substrate; the connection line includes a first line portion formed on the electrode layer and a second line portion formed on the first metal layer; the first line portion is electrically connected to the second line portion; at least part of the first line portion is arranged in a clock signal line area, the first driving circuit portion and the line collection portion; the clock signal line area is an area where the plurality of clock signal lines are arranged; at least part of the second line portion is arranged on the line collection portion.

6. The display substrate according to claim 1 , wherein the driving circuit includes an input circuit; a control terminal of the input circuit and/or a first terminal of the input circuit are electrically connected to an input terminal, and a second terminal of the input circuit is electrically connected to the pull-up node;
the input circuit is configured to control the potential of the pull-up node under the control of an input signal provided by the input terminal.

7. The display substrate according to claim 6 , wherein the input circuit includes a first transistor;
a gate electrode of the first transistor is electrically connected to a first input terminal, a first electrode of the first transistor is electrically connected to a second input terminal, and a second electrode of the first transistor is electrically connected to the pull-up node;
the first input terminal and the second input terminal are electrically connected or not electrically connected.

8. The display substrate according to claim 7 , wherein the gate electrode of the first transistor is formed on a second metal layer, and the first electrode of the first transistor is formed on a first metal layer;
the gate electrode of the first transistor is electrically connected to a first connection line portion formed on the second metal layer;
the first electrode of the first transistor is electrically connected to a second connection line portion formed on the second metal layer through a via hole;
the connection line includes a third connection line portion formed on the electrode layer and a fourth connection line portion formed on the first metal layer; the third connection line portion is electrically connected to the fourth connection line portion;
there is an overlapping portion between an orthographic projection of the third connection line portion on the base substrate and an orthographic projection of the first connection line portion on the base substrate; there is an overlapping portion between an orthographic projection of the fourth connection line portion on the base substrate and an orthographic projection of the second connection line portion on the base substrate.

9. The display substrate according to claim 8 , further comprising a fifth connection line portion and a sixth connection line portion; wherein
the fifth connection line portion is formed on the electrode layer, and the fifth connection line portion is connected to the third connection line portion;
the sixth connection line portion is formed on the first metal layer, and the sixth connection line portion is connected to the fourth connection line portion;
the fifth connection line portion is electrically connected to the sixth connection line portion;
or
the display substrate further includes a fifth connection line portion;
the fifth connection line portion is formed on the electrode layer, and the fifth connection line portion is connected to the third connection line portion.

10. The display substrate according to claim 1 , wherein the driving circuit further includes an output reset circuit and at least one clock signal line;
a control terminal of the output reset circuit is electrically connected to a reset control terminal, a first terminal of the output reset circuit is electrically connected to a driving signal output terminal of a current stage, and a second terminal of the output reset circuit is electrically connected to the first voltage line, the output reset circuit is configured to control to connect the driving signal output terminal of the current stage and the first voltage line under the control of a reset control signal provided by the reset control terminal;
there is an overlapping portion between the orthographic projection of the connection line on the base

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhou Maoxiu
• Guo Lei
• Dai Ke
• Zhang Chunxu
• Cheng Min
• Jiang Xiaoting
• Yang Haipeng

Classifications

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title