Integrated circuit layout including standard cells and method to form the same

Patent metadata

Field	Value
Publication number	US-12406125-B2
Application number	US-202217868770-A
Country	US
Kind code	B2
Filing date	Jul 19, 2022
Priority date	Sep 28, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

First claim

What is claimed is:

1. An integrated circuit layout, comprising:
a power rail and a ground rail extending in parallel along a first direction; and
a first standard cell and a second standard cell abutted to each other side by side between the power rail and the ground rail, which respectively comprising:
an upper edge, a lower edge, and a well boundary between the upper edge and the lower edge extending in parallel along the first direction;
two active regions of opposite conductivity types at two sides of the well boundary; and
a gate line extending between the upper edge and the lower edge along a second direction and intersecting the two active regions, wherein the first direction and the second direction are perpendicular;

wherein a first cell height between the upper edge and lower edge of the first cell and a second cell height between the upper edge and lower edge of the second standard cell are different, the well boundaries of the first standard cell and the second standard cell are aligned along the first direction.

2. The integrated circuit layout according to claim 1 , wherein a centerline between the upper edge and the lower edge of the first standard cell and a centerline between the upper edge and the lower edge of the second standard cell are aligned along the first direction.

3. The integrated circuit layout according to claim 2 , wherein the centerline and the well boundary of each of the first standard cell and the second standard cell are overlapped.

4. The integrated circuit layout according to claim 2 , wherein the centerline and the well boundary of each of the first standard cell and the second standard cell are not overlapped.

5. The integrated circuit layout according to claim 1 , wherein a distance between the power rail and the upper edge of the second standard cell is larger than a distance between the power rail and the upper edge of the first standard cell.

6. The integrated circuit layout according to claim 1 , wherein a centerline between the upper edge and the lower edge of the first standard cell and a centerline between the upper edge and the lower edge of the second standard cell are offset along the first direction, and a distance between the power rail and the upper edge of the second standard cell is different from a distance between the ground rail and the lower edge of the second standard cell.

7. The integrated circuit layout according to claim 1 , wherein edges of the active regions of a same conductivity type of the first standard cell and the second standard cell adjacent and parallel to the well boundary are aligned along the first direction.

8. The integrated circuit layout according to claim 1 , wherein edges of the active regions of a same conductivity type of the first standard cell and the second standard cell adjacent to the well boundary are offset along the first direction.

9. The integrated circuit layout according to claim 8 , further comprising:
a first conductive connector extending from an edge of the power rail along the second direction a first length to partially overlap one of the active regions of the first standard cell; and
a second conductive connector extending from the edge of the power rail a second length to partially overlap one of the active regions of the second standard cell,
wherein the first length and the second length are different.

10. The integrated circuit layout according to claim 1 , further comprising:
a first dummy gate line at a side of the first standard cell opposite to the second standard cell;
a second dummy gate line at a side of the second standard cell opposite to the first standard cell; and
a third dummy gate line between the first standard cell and the second standard cell, wherein the first dummy gate line and the third dummy gate line have line ends flush with line ends of the gate line of the first standard cell, the second dummy gate line has line ends flush with line ends of the gate line of the second standard cell.

Assignees

• United Microelectronics Corp

Inventors

• Chen Chien-Hung
• Chen Ruei-Yau
• Wang Wei-Jen
• Wu Kun-Yuan
• Chen Chien-Fu
• Hsu Chen-Hsien

Classifications

• H10W20/427

  Power or ground buses · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title