Voltage detector in data communication interface

Patent metadata

Field	Value
Publication number	US-12405622-B2
Application number	US-202318498927-A
Country	US
Kind code	B2
Filing date	Oct 31, 2023
Priority date	Jul 17, 2023
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

Mechanisms for detecting a voltage level on a data communication interface between a slave device and a host device are disclosed. Based on the detected voltage level, the slave device may respond to the host device on the data communication interface at the detected voltage level. The slave device may include a circuit configured to toggle between a first voltage level and a second voltage level to provide one of the first voltage level or the second voltage level corresponding to the detected voltage level on the data communication interface.

First claim

What is claimed is:

1. An apparatus, comprising:
a clock line voltage detector configured to detect a voltage level of a clock signal sent by a host device on a clock line of a data communication interface between the apparatus and the host device, wherein the voltage level comprises a first voltage level or a second voltage level, wherein the first voltage level is higher than the second voltage level, wherein the clock line voltage detector comprises:
a comparator configured to compare a clock line voltage of the clock signal with a threshold voltage to produce a comparator output indicative of the detected voltage level; and
a low pass filter configured to filter the clock signal and to provide a filtered clock signal to the comparator, wherein a cutoff frequency of the low pass filter is set to a multiple of the first voltage level to prevent false detection of the first voltage level by the comparator; and

a circuit configured to provide an output voltage on the data communication interface, the output voltage being one of the first voltage level or the second voltage level corresponding to the detected voltage level.

2. The apparatus of claim 1 , wherein the first voltage level is 1.8 V and the second voltage level is 1.2 V.

3. The apparatus of claim 1 , wherein the circuit is configured to receive the comparator output and to select the first voltage level or the second voltage level based on the comparator output.

4. The apparatus of claim 1 , wherein the clock line voltage detector further comprises a level shifter configured to produce a clock level signal based on the comparator output and to provide the clock level signal to the circuit.

5. The apparatus of claim 1 , wherein the threshold voltage is between the first voltage level and the second voltage level.

6. The apparatus of claim 5 , wherein the threshold voltage is between 1.3 V and 1.4 V.

7. The apparatus of claim 1 , wherein the circuit comprises a low drop-out (LDO) regulator.

8. The apparatus of claim 7 , wherein the LDO regulator is configured to receive a supply voltage at the first voltage level, to pass the supply voltage at the first voltage level through the LDO regulator as the output voltage in response to the detected voltage level being the first voltage level, and to regulate the supply voltage down to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

9. A method operable at a slave device, the method comprising:
detecting a voltage level of a clock signal sent by a host device on a clock line of a data communication interface between the slave device and the host device, wherein the voltage level comprises a first voltage level or a second voltage level, wherein the first voltage level is higher than the second voltage level, wherein the detecting the voltage level comprises:
filtering the clock signal using a low pass filter to produce a filtered clock signal; and
comparing a clock line voltage of the filtered clock signal with a threshold voltage to produce a comparator output indicative of the detected voltage level, wherein a cutoff frequency of the low pass filter is set to a multiple of the first voltage level to prevent false detection of the first voltage level; and

providing an output voltage on the data communication interface, the output voltage being at one of the first voltage level or the second voltage level corresponding to the detected voltage level.

10. The method of claim 9 , wherein the first voltage level is 1.8 V and the second voltage level is 1.2 V.

11. The method of claim 9 , further comprising:
selecting the first voltage level or the second voltage level based on the comparator output.

12. The method of claim 9 , further comprising:
producing a clock level signal based on the comparator output; and
selecting one of the first voltage level or the second voltage level based on the clock level signal.

13. The method of claim 9 , wherein the threshold voltage is between the first voltage level and the second voltage level.

14. The method of claim 13 , wherein the threshold voltage is between 1.3 V and 1.4 V.

15. The method of claim 9 , further comprising:
receiving a supply voltage at the first voltage level;
passing the supply voltage at the first voltage level as the output voltage in response to the detected voltage level being the first voltage level; and
regulating the supply voltage down to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

16. A slave device, comprising:
means for detecting a voltage level of a clock signal sent by a host device on a clock line of a data communication interface between the slave device and the host device, wherein the voltage level comprises a first voltage level or a second voltage level, wherein the first voltage level is higher than the second voltage level, wherein the means for detecting the voltage level comprises:
means for filtering the clock signal using a low pass filter to produce a filtered clock signal; and
means for comparing a clock line voltage of the filtered clock signal with a threshold voltage to produce a comparator output indicative of the detected voltage level, wherein a cutoff frequency of the low pass filter is set to a multiple of the first voltage level to prevent false detection of the first voltage level; and

means for providing an output voltage on the data communication interface, the output voltage being one of a first voltage level or a second voltage level corresponding to the detected voltage level.

17. The slave device of claim 16 , wherein the first voltage level is 1.8 V and the second voltage level is 1.2 V.

18. The slave device of claim 16 , further comprising:
means for selecting the first voltage level or the second voltage level based on the comparator output.

19. The slave device of claim 16 , further comprising:
means for producing a clock level signal based on the comparator output; and
means for selecting one of the first voltage level or the second voltage level based on the clock level signal.

20. The slave device of claim 16 , wherein the threshold voltage is between the first voltage level and the second voltage level.

21. The slave device of claim 20 , wherein the threshold voltage is between 1.3 V and 1.4 V.

22. The slave device of claim 16 , further comprising:
means for receiving a supply voltage at the first voltage level;
means for passing the supply voltage at the first voltage level as the output voltage in response to the detected voltage level being the first voltage level; and
means for regulating the supply voltage down to the second voltage level to provide the output voltage at the second voltage level to the data communication interface.

Assignees

• Qualcomm Inc

Inventors

• Gustavsson Bengt Stefan
• Oliveira Louis Dominic
• Saraf Tomer
• Littrell Robert John
• Kiran Ganesh
• Kuo William Wei-Ting

Classifications

• H03K5/24

  the characteristic being amplitude · CPC title

• H03K5/125 Primary

  Discriminating pulses (measuring characteristics of individual pulses G01R29/02; separation of synchronising signals in television systems H04N5/08) · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title