Voltage sampler and solid-state transformer

Patent metadata

Field	Value
Publication number	US-12405292-B2
Application number	US-202217850459-A
Country	US
Kind code	B2
Filing date	Jun 27, 2022
Priority date	Jun 28, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

This application provides a voltage sampler and a solid-state transformer. The voltage sampler includes a conductive housing, at least one sampling board located inside the housing, and a conducting layer. Each sampling board includes at least two resistors and a voltage input end. The resistors in the sampling board are electrically connected in sequence in the direction from a first end to a second end. The resistor at the first end is electrically connected to the voltage input end. The resistor at the second end is electrically connected to the housing, and the housing is electrically connected to a fixed potential end. The conducting layer is disposed between the at least one sampling board and the housing in the voltage sampler. The conducting layer is electrically connected to a resistor in the sampling board.

First claim

What is claimed is:

1. A voltage sampler, comprising a conductive housing, at least one sampling board located inside the housing, and a conducting layer, wherein
each of the at least one sampling board comprises at least two resistors and a voltage input end, the at least two resistors are electrically connected in sequence in a direction from a first end to a second end, a resistor at the first end is electrically connected to the voltage input end, a resistor at the second end is electrically connected to the housing, the housing is electrically connected to a fixed potential end; and
the conducting layer is disposed between at least one of the at least one sampling board and the housing, the conducting layer is electrically connected to one of the at least two resistors in the sampling board.

2. The voltage sampler according to claim 1 , further comprising an insulator located inside the housing, wherein
at least one cavity configured to accommodate the at least one sampling board is disposed in the insulator, and there is a gap between each of the at least one sampling board and the insulator.

3. The voltage sampler according to claim 2 , wherein one sampling board is disposed in each of the at least one cavity.

4. The voltage sampler according to claim 3 , wherein at least two cavities connected to each other are disposed in the insulator.

5. The voltage sampler according to claim 2 , wherein the conducting layer is disposed on an inner wall of the cavity, and an insulation film is disposed on a surface on a side that is of the conducting layer and that faces the sampling board.

6. The voltage sampler according to claim 2 , wherein the conducting layer is embedded inside the insulator.

7. The voltage sampler according to claim 2 , wherein the insulator comprises a first insulation portion and a second insulation portion fixedly connected to the first insulation portion;
the first insulation portion comprises a groove configured to accommodate the sampling board; and
the groove in the first insulation portion and the second insulation portion form the at least one cavity.

8. The voltage sampler according to claim 3 , wherein the insulator comprises a first insulation portion and a second insulation portion fixedly connected to the first insulation portion;
the first insulation portion comprises a groove configured to accommodate the sampling board; and
the groove in the first insulation portion and the second insulation portion form the at least one cavity.

9. The voltage sampler according to claim 4 , wherein the insulator comprises a first insulation portion and a second insulation portion fixedly connected to the first insulation portion;
the first insulation portion comprises a groove configured to accommodate the sampling board; and
the groove in the first insulation portion and the second insulation portion form the at least one cavity.

10. The voltage sampler according to claim 5 , wherein the insulator comprises a first insulation portion and a second insulation portion fixedly connected to the first insulation portion;
the first insulation portion comprises a groove configured to accommodate the sampling board; and
the groove in the first insulation portion and the second insulation portion form the at least one cavity.

11. The voltage sampler according to claim 7 , wherein a strip-shaped groove is disposed at the top of a side wall of the groove in the first insulation portion, a strip-shaped protrusion corresponding to a location of the strip-shaped groove is disposed in the second insulation portion, and the strip-shaped protrusion is embedded in the corresponding strip-shaped groove.

12. The voltage sampler according to claim 7 , wherein a strip-shaped protrusion is disposed at the top of a side wall of the groove in the first insulation portion, a strip-shaped groove corresponding to a location of the strip-shaped protrusion is disposed in the second insulation portion, and the strip-shaped protrusion is embedded in the corresponding strip-shaped groove.

13. The voltage sampler according to claim 7 , wherein the conducting layer is disposed on an inner bottom surface and an inner side surface of the groove in the first insulation portion.

14. The voltage sampler according to claim 1 , wherein one conducting layer is disposed between at least one of the at least one sampling board and the housing; and
an orthographic projection of the conducting layer on the at least one sampling board covers at least half of the at least two resistors in the sampling board, the orthographic projection of the conducting layer on the sampling board covers the resistor located at the first end, and the potential of the conducting layer is greater than ½ of the potential of the voltage input end.

15. The voltage sampler according to claim 14 , wherein the orthographic projection of the conducting layer on the sampling board covers 2n/3 resistors, and the potential of the conducting layer is equal to ⅔ of the potential of the voltage input end, wherein n is a quantity of resistors in the sampling board, and n is a multiple of 3.

16. The voltage sampler according to claim 1 , wherein two conducting layers are disposed between at least one of the at least one sampling board and the housing: a first conducting layer and a second conducting layer;
an orthographic projection of the first conducting layer on the sampling board covers some of the at least two resistors in the sampling board, an orthographic projection of the second conducting layer on the sampling board covers the other resistors in the sampling board, and the orthographic projection of the first conducting layer on the sampling board covers the resistor at the first end; and
a potential of the first conducting layer is greater than that of the second conducting layer.

17. The voltage sampler according to claim 16 , wherein the orthographic projection of the first conducting layer on the at least one sampling board covers n/2 resistors in the sampling board, and the orthographic projection of the second conducting layer on the at least one sampling board covers the other n/2 resistors in the sampling board; and
the potential of the first conducting layer is greater than ½ of the potential of the voltage input end, and the potential of the second conducting layer is less than ½ of the potential of the voltage input end, wherein
n is a quantity of resistors in the at least one sampling board, and n is a multiple of 2.

18. The voltage sampler according to claim 16 , wherein a bent portion is disposed at an end that is of the first conducting layer and that is close to the second conducting layer, and the bent portion is bent toward the housing.

19. The voltage sampler according to claim 16 , wherein a bent portion is disposed at an end that is of the second conducting layer and that is close to the first conducting layer, and the bent portion is bent toward the housing.

20. A solid-state transformer, comprising a voltage sampler, and a power converter electrically connected to the voltage sampler; wherein the voltage sampler comprises a conductive housing, at least one sampling board located inside the housing, and a conducting layer, wherein
each of the at least one sampling board comprises at least two resistors and a voltage input end, the at least two resistors are electrically connected in sequence in a direction from a first end to a second end, a resistor at the first end is electrically connected to the voltage input end, a resistor at the s

Assignees

• Huawei Digital Power Tech Co Ltd

Inventors

• Huang Zhuyong
• Zhang Xiaofei
• Shuai Peng

Classifications

• H01F27/42

  Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils (circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H) · CPC title

• H01C1/16

  Resistor networks not otherwise provided for · CPC title

• H01B17/62

  Insulating-layers or insulating-films on metal bodies · CPC title

• H01B17/005

  Insulators structurally associated with built-in electrical equipment · CPC title

• H01B5/02

  Single bars, rods, wires, or strips · CPC title