Digital to analog converter

Patent metadata

Field	Value
Publication number	US-12401370-B2
Application number	US-202318314529-A
Country	US
Kind code	B2
Filing date	May 9, 2023
Priority date	May 20, 2022
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

In an embodiment a digital-to-analog converter includes a plurality of first capacitors, each having a first electrode and a second electrode, wherein the second electrodes are connected together and are connected to an inverting input of a first amplifier stage having its non-inverting input coupled to ground, a plurality of first switches, each of the first capacitors having its first electrode connected to a corresponding one of the first switches, wherein each of the first switches is configured to occupy a first state where the first electrode of a corresponding first capacitor is coupled to a first reference voltage and occupy a second state where the first electrode of the corresponding first capacitor is coupled to a second reference voltage different from the first reference voltage, a capacitive feedback circuit connected between the inverting input and an output of the first amplifier stage, the capacitive feedback circuit including at least one second capacitor and a controller.

First claim

What is claimed is:

1. A digital-to-analog converter comprising:
a plurality of first capacitors, each having a first electrode and a second electrode, wherein the second electrodes are connected together and are connected to an inverting input of a first amplifier stage having its non-inverting input coupled to ground;
a plurality of first switches, each of the first capacitors having its first electrode connected to a corresponding one of the first switches,
wherein each of the first switches is configured to:
occupy a first state where the first electrode of a corresponding first capacitor is coupled to a first reference voltage, and
occupy a second state where the first electrode of the corresponding first capacitor is coupled to a second reference voltage different from the first reference voltage;

a capacitive feedback circuit connected between the inverting input and an output of the first amplifier stage, the capacitive feedback circuit comprising at least one second capacitor; and
a controller configured to:
control the plurality of first switches, and
modify a charge accumulated in the capacitive feedback circuit and therefore generate a sequence comprising one or more voltage ramps at the output of the first amplifier stage.

2. The converter according to claim 1 , further comprising:
a reset circuit configured to reset the at least one second capacitor, the reset circuit connected to the inverting input and to the output of the first amplifier stage,
wherein the reset circuit comprises a switch connected to the inverting input of the first amplifier stage, and
wherein the output of the first amplifier stage is controlled by a reset voltage value when the switch of the reset circuit is on.

3. The converter according to claim 2 , wherein the switch of the reset circuit is further connected to an output of a second amplifier, wherein the reset voltage is a third reference voltage applicable to an input of the second amplifier, and wherein an inverting input of the second amplifier is connected to the output of the first amplifier stage.

4. The converter according to claim 1 , wherein the controller is configured to control the first switches one after another to progressively modify the charge accumulated at a level of the capacitive feedback circuit and therefore generate the one or more voltage ramps of the sequence.

5. The converter according to claim 1 , wherein the controller comprises one or more shift registers configured to control the plurality of first switches.

6. The converter according to claim 1 , wherein the controller is configured to simultaneously control the plurality of first switches in order to generate a voltage jump at the output of the first amplifier stage.

7. The converter according to claim 1 , wherein a number of the first capacitors is greater than or equal to 2n, and wherein n is an integer greater than or equal to 6.

8. The converter according to claim 1 , wherein the first capacitors have an equal or approximately equal capacitance.

9. The converter according to claim 1 , wherein the controller is configured to select relative levels of the first and second reference voltages to select a positive slope or a negative slope of the one or more voltage ramps of the sequence.

10. The converter according to claim 1 , wherein the controller further comprises addressing means for programmably controlling the plurality of first switches.

11. An image sensor comprising:
a pixel array; and
at least one digital-to-analog converter according to claim 1 ,
wherein the at least one digital-to-analog converter is coupled to the pixel array.

12. A method for generating a sequence of one or more voltage ramps, the method comprising:
controlling, by a controller, a plurality of first switches of a digital-to-analog converter,
wherein the digital-to-analog converter comprises:
a plurality of first capacitors, each having a first electrode and a second electrode,
wherein the second electrodes are connected together and are connected to an inverting input of a first amplifier stage having its non-inverting input coupled to ground,
wherein each of the first capacitors has its first electrode connected to a corresponding one of the first switches, and
wherein each of the first switches is capable of occupying a first state where the first electrode of a corresponding first capacitor is coupled to a first reference voltage, and occupying a second state where the first electrode of the corresponding first capacitor is coupled to a second reference voltage different from the first reference voltage, and
a capacitive feedback circuit comprising at least one second capacitor connected between the inverting input and an output of the first amplifier stage, and
wherein the first switches are controlled in order to modify a charge accumulated in the capacitive feedback circuit and therefore in order to generate the sequence at the output of the first amplifier stage of the digital-to-analog converter.

13. The method according to claim 12 , further comprising
resetting, by a resetting circuit, the at least one second capacitor, wherein the resetting circuit is connected to the inverting input and to the output of the first amplifier stage, wherein the reset circuit comprises a switch connected to the inverting input of the first amplifier stage, and wherein the output of the first amplifier stage is controlled by a value of a reset voltage.

14. The method according to claim 13 , wherein the switch of the reset circuit is further connected to an output of a second amplifier, wherein the reset voltage is a third reference voltage applied to an input of the second amplifier, and wherein an inverting input of the second amplifier is connected to the output of the first amplifier stage.

15. The method according to claim 12 , wherein the first switches are controlled one after another to progressively modify the charge accumulated at a level of the capacitive feedback circuit and therefore to generate the one or more voltage ramps of the sequence.

16. The method according to claim 12 , wherein the controller comprises one or more shift registers to control the plurality of first switches.

17. The method according to claim 12 , wherein the controller simultaneously controls the plurality of first switches to generate a voltage jump at the output of the first amplifier stage.

18. The method according to claim 12 , wherein a number of the first capacitors is greater than or equal to 2n, and wherein n is an integer greater than or equal to 6.

19. The method according to claim 12 , wherein the first capacitors have an equal or approximately equal capacitance.

20. The method according to claim 12 , wherein the controller selects relative levels of the first and second reference voltages to select a positive slope or a negative slope of the one or more voltage ramps of the sequence.

Assignees

• St Microelectronics Grenoble 2

Inventors

• Simony Laurent

Classifications

• H04N25/70

  SSIS architectures; Circuits associated therewith · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03K4/56

  using a semiconductor device with negative feedback through a capacitor, e.g. Miller integrator · CPC title

• H03M1/0845 Primary

  of power supply variations, e.g. ripple · CPC title

• H03K4/026 Primary

  using digital techniques · CPC title