PUF circuit based on threshold loss of MOSFETs

Patent metadata

Field	Value
Publication number	US-12401362-B2
Application number	US-202318476303-A
Country	US
Kind code	B2
Filing date	Sep 27, 2023
Priority date	Jul 28, 2023
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.

First claim

What is claimed is:

1. A PUF circuit based on a threshold loss of MOSFETs comprises N stages of delay units and an arbiter, wherein N=2 m , m is an integer which is greater than or equal to 6, the N stages of delay units are identical in structure and are cascaded in sequence, the N stages of delay units are sequentially referred to as a first stage of delay unit to an N th stage of delay unit, the N th stage of delay unit is connected to the arbiter, each stage of delay unit is configured to allow two square signals input thereto to pass through in parallel or in a crossed manner under the control of a control signal input to the stage of delay unit to generate and output two square signals, the two square signals generated by the prior stage of delay unit are output to the next stage of delay unit, and the arbiter is configured to extracting, by comparison, a delay difference between the two square signals outputted by the N th stage of delay unit to generate and output a response; characterized in that each of the delay units comprises six inverters and four MOS transistors, the four MOS transistors are all PMOS transistors or NMOS transistors, the six inverters are referred to as a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a sixth inverter respectively, the four MOS transistors are referred to as a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor respectively, an input terminal of the first inverter is used as a first input terminal of the each of delay units to receive a first path square signal, an input terminal of the fourth inverter is used as a second input terminal of the each of the delay units to receive a second path square signal, an output terminal of the first inverter, a source of the first MOS transistor and a source of the second MOS transistor are connected, an output terminal of the fourth inverter, a source of the third MOS transistor and a source of the fourth MOS transistor are connected, a drain of the first MOS transistor, a drain of the fourth MOS transistor and an input terminal of the third inverter are connected, a drain of the second MOS transistor, a drain of the third MOS transistor and an input terminal of the sixth inverter are connected, a gate of the first MOS transistor, an input terminal of the second inverter, a gate of the third MOS transistor and an input terminal of the fifth inverter are connected and a connecting terminal is used as a control terminal of the each of the delay units to receive a control signal, an output terminal of the second inverter and a gate of the second MOS transistor are connected, an output terminal of the fifth inverter and a gate of the fourth MOS transistor are connected, and an output terminal of the third inverter and an output terminal of the sixth inverter are used as two output terminals of the each of the delay units to generate and output the two square signals.

2. The PUF circuit based on the threshold loss of MOSFETs, according to claim 1 , wherein when the four MOS transistors are all PMOS transistors, the arbiter comprises two two-input NAND gates, each two-input NAND gate has a first input terminal, a second input terminal and an output terminal, the two two-input NAND gates are referred to as a first two-input NAND gate and a second two-input NAND gate respectively, the first input terminal of the first two-input NAND gate and the second input terminal of the second two-input NAND gate are configured to receive the two square signals outputted by the N th stage of delay unit respectively, the second input terminal of the first two-input NAND gate and the output terminal of the second two-input NAND gate are connected and a connecting terminal is used as an output terminal of the arbiter to output the response, and the output terminal of the first two-input NAND gate and the first input terminal of the second two-input NAND gate are connected.

3. The PUF circuit based on the threshold loss of MOSFETs, according to claim 1 , wherein when the four MOS transistors are all NMOS transistors, the arbiter comprises two two-input NOR gates, wherein each two-input NOR gate has a first input terminal, a second input terminal and an output terminal, the two two-input NOR gates are referred to as a first two-input NOR gate and a second two-input NOR gate respectively, the first input terminal of the first two-input NOR gate and the second input terminal of the second two-input NOR gate are used for receive the two square signals outputted by the N th stage of delay unit respectively, the second input terminal of the first two-input NOR gate and the output terminal of the second two-input NOR gate are connected and a connecting terminal is used as an output terminal of the arbiter to output the response, and the output terminal of the first two-input NOR gate and the first input terminal of the second two-input NOR gate are connected.

Assignees

• Univ Wenzhou

Inventors

• Li Gang
• Wang Pengjun
• Shao Xilong
• Li Hui
• Zhou Junjie

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K5/133 Primary

  using a chain of active delay devices · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title

• H03K19/00315 Primary

  in field-effect transistor circuits · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title