Hybrid filter on chip with integrated passive device (IPD) and film bulk acoustic resonator (FBAR)

Patent metadata

Field	Value
Publication number	US-12401344-B2
Application number	US-202519017865-A
Country	US
Kind code	B2
Filing date	Jan 13, 2025
Priority date	Nov 17, 2023
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A method for preparing a hybrid filter on a chip with IPD and FBAR, includes: preparing a leakage isolation layer on a supporting substrate by deposition; obtaining an inductor layer on the leakage isolation layer, leaving a window at a bottom of a groove surrounding a cross section of a TGV inductor stack on a mask, and patterning an inductor metal simultaneously; forming a first insulating layer on the inductor metal, and forming lead through holes by photolithography; repeating steps and alternately to obtain a three-layer stacked TGV inductor; depositing a second insulating layer on the TGV inductor; depositing two capacitor layers on the second insulating layer, and depositing a third insulating layer between the two capacitor layers to form an MIM capacitor; and preparing a BAW resonator on the MIM capacitor, and connecting the TGV inductor, the MIM capacitor and the BAW resonator through the lead through holes.

First claim

The invention claimed is:

1. A method for preparing a hybrid filter on a chip with an integrated passive device (IPD) and a film bulk acoustic resonator (FBAR), comprising:
(1) preparing a leakage isolation layer on a supporting substrate by deposition;
(2) obtaining an inductor layer by first physical vapor deposition on the leakage isolation layer prepared in step (1), leaving a window at a bottom of a groove surrounding a cross section of a through glass via (TGV) inductor stack on a mask, and patterning an inductor metal simultaneously;
(3) forming a first insulating layer on the inductor metal prepared in step (2) by first chemical vapor deposition, and forming lead through holes by photolithography;
(4) repeating steps (2) and (3) alternately to obtain a three-layer stacked TGV inductor;
(5) depositing a second insulating layer on the three-layer stacked TGV inductor prepared in step (4) by second chemical vapor deposition to serve as a partition between a capacitor layer and the three-layer stacked TGV inductor;
(6) depositing two capacitor layers on the second insulating layer deposited in step (5) by second physical vapor deposition, and depositing a third insulating layer between the two capacitor layers to form a metal insulator metal (MIM) capacitor; and
(7) preparing a bulk acoustic wave (BAW) resonator on the MIM capacitor prepared in step (6), and connecting the three-layer stacked TGV inductor, the MIM capacitor and the BAW resonator through the lead through holes to obtain the hybrid filter.

2. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 1 , wherein the BAW resonator comprises a bottom electrode, a piezoelectric layer, a top electrode and an anti-oxidation layer arranged in sequence, and an air gap is formed between the bottom electrode and the MIM capacitor.

3. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 2 , wherein a material of the bottom electrode and the top electrode is one or more of aluminum, molybdenum, tungsten, platinum, titanium, and gold.

4. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 2 , wherein a material of the piezoelectric layer is single-crystalline aluminum nitride, or polycrystalline aluminum nitride, or zinc oxide, or lead zirconate titanate, or barium strontium titanate (BST), or LiNbO 3 .

5. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 2 , wherein a material of the anti-oxidation layer is aluminum nitride.

6. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 1 , wherein a material of the supporting substrate is silicon, sapphire, LiGaO 2 , or metal.

7. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 1 , wherein a material of the leakage isolation layer is gallium arsenide.

8. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 1 , wherein a material of each of the first insulating layer, the second insulating layer and the third insulating layer is silicon dioxide.

9. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 1 , wherein a material of each of the lead through holes is gold, copper, or molybdenum.

10. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 1 , wherein a material of the inductor layer is copper.

11. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 1 , wherein a material of each of the two capacitor layers is copper.

12. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 2 , wherein a material of the supporting substrate is silicon, sapphire, LiGaO 2 , or metal.

13. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 3 , wherein a material of the supporting substrate is silicon, sapphire, LiGaO 2 , or metal.

14. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 4 , wherein a material of the supporting substrate is silicon, sapphire, LiGaO 2 , or metal.

15. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 5 , wherein a material of the supporting substrate is silicon, sapphire, LiGaO 2 , or metal.

16. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 2 , wherein a material of the leakage isolation layer is gallium arsenide.

17. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 3 , wherein a material of the leakage isolation layer is gallium arsenide.

18. The method for preparing the hybrid filter on the chip with the IPD and the FBAR according to claim 4 , wherein a material of the leakage isolation layer is gallium arsenide.

Assignees

• Univ South China Tech

Inventors

• Li Guoqiang
• Xu Kaibin
• Chen Zhipeng
• Hu Han
• Zhu Yuhan

Classifications

• H03H9/173 Primary

  Air-gaps · CPC title

• H03H3/02

  for the manufacture of piezoelectric or electrostrictive resonators or networks (H03H3/08 takes precedence) · CPC title

• H03H9/0542

  consisting of a lateral arrangement (H03H9/0566 takes precedence) · CPC title

• H03H2003/021

  the resonators or networks being of the air-gap type · CPC title

• H03H9/542 Primary

  including passive elements (H03H9/545 takes precedence) · CPC title