Low parasitic equivalent series L-inductance (ESL) symmetric direct current (DC) link capacitor

US12400797B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12400797-B2
Application numberUS-202318308201-A
CountryUS
Kind codeB2
Filing dateApr 27, 2023
Priority dateApr 27, 2023
Publication dateAug 26, 2025
Grant dateAug 26, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Aspects of the disclosure include a symmetric direct current (DC) link capacitor having a low parasitic equivalent series L-inductance (ESL). An exemplary capacitor can include one or more positive-dielectric-negative (PDN) stacks having a positive layer, a negative layer, and a dielectric layer between the positive layer and the negative layer. A first contact layer is electrically coupled to the positive layer on a sidewall of the one or more PDN stacks and a second contact layer is electrically coupled to the negative layer on the sidewall of the one or more PDN stacks. A positive terminal is electrically coupled to the first contact layer and a negative terminal is electrically coupled to the second contact layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A vehicle comprising: an electric motor; a battery pack electrically coupled to the electric motor; a converter configured to convert a direct current at a first voltage from the battery pack to a direct current at a second voltage lower than the first voltage; an inverter configured to convert the direct current from the battery pack to an alternating current supplied to the electric motor; and a capacitor electrically coupled to at least one of the inverter and the converter of the vehicle, the capacitor comprising one or more capacitor modules comprising: a plurality of vertically stacked positive-dielectric-negative (PDN) stacks, each PDN stack comprising a positive layer, a negative layer, and a dielectric layer between the positive layer and the negative layer, wherein the positive layer comprises a first protruding portion and the negative layer comprises a second protruding portion, each of the PDN stacks configured such that all first protruding portions and all second protruding portions extend from a same side of the capacitor; a first contact layer electrically coupled to the first protruding portion of all of the positive layers, the first contact layer on a sidewall of the PDN stacks; a second contact layer electrically coupled to the second protruding portion of all of the negative layers, the second contact layer on the sidewall of the PDN stacks; a positive terminal electrically coupled to the first contact layer; and a negative terminal electrically coupled to the second contact layer. 2. The vehicle of claim 1 , wherein each of the PDN stacks comprises a bottom dielectric layer, wherein the negative layer is between the dielectric layer and the bottom dielectric layer. 3. The vehicle of claim 1 , wherein the positive layer and the negative layer each comprise one of a single-sided metalized film and a double-sided metalized film. 4. The vehicle of claim 1 , wherein the positive terminal and the negative terminal collectively define a busbar of the capacitor. 5. The vehicle of claim 4 , wherein the positive terminal and the negative terminal are positioned vertically and in parallel on a same sidewall of the PDN stacks as the first contact layer and the second contact layer. 6. The vehicle of claim 1 , wherein the first protruding portion and the second protruding portion are offset with respect to one another such that the first protruding portion and the second protruding portion do not overlap. 7. A capacitor comprising: a plurality of vertically stacked positive-dielectric-negative (PDN) stacks, each PDN stack comprising a positive layer, a negative layer, and a dielectric layer between the positive layer and the negative layer, wherein the positive layer comprises a first protruding portion and the negative layer comprises a second protruding portion, each of the PDN stacks configured such that all first protruding portions and all second protruding portions extend from a same side of the capacitor; a first contact layer electrically coupled to the first protruding portion of all of the positive layers, the first contact layer on a sidewall of the one or more PDN stacks; a second contact layer electrically coupled to the second protruding portion of all of the negative layers, the second contact layer on the sidewall of the one or more PDN stacks; a positive terminal electrically coupled to the first contact layer; and a negative terminal electrically coupled to the second contact layer. 8. The capacitor of claim 7 , wherein each of the PDN stacks comprises a bottom dielectric layer, wherein the negative layer is between the dielectric layer and the bottom dielectric layer. 9. The capacitor of claim 7 , wherein the positive layer and the negative layer each comprise one of a single-sided metalized film and a double-sided metalized film. 10. The capacitor of claim 7 , wherein the positive terminal and the negative terminal collectively define a busbar of the capacitor. 11. The capacitor of claim 10 , wherein the positive terminal and the negative terminal are positioned vertically and in parallel on a same sidewall of the PDN stacks as the first contact layer and the second contact layer. 12. The capacitor of claim 7 , wherein the first protruding portion and the second protruding portion are offset with respect to one another such that the first protruding portion and the second protruding portion do not overlap. 13. A method for reducing a parasitic equivalent series L-inductance (ESL) of a capacitor, the method comprising: forming a plurality of vertically stacked positive-dielectric-negative (PDN) stacks, each PDN stack comprising a positive layer, a negative layer, and a dielectric layer between the positive layer and the negative layer, wherein the positive layer comprises a first protruding portion and the negative layer comprises a second protruding portion, each of the PDN stacks configured such that all first protruding portions and all second protruding portions extend from a same side of the capacitor; electrically coupling a first contact layer to the first protruding portion of all of the positive layers, the first contact layer on a sidewall of the PDN stacks; electrically coupling a second contact layer to the second protruding portion of all of the negative layers, the second contact layer on the sidewall of the PDN stacks; electrically coupling a positive terminal to the first contact layer; and electrically coupling a negative terminal to the second contact layer. 14. The method of claim 13 , wherein each of the PDN stacks comprises a bottom dielectric layer, wherein the negative layer is between the dielectric layer and the bottom dielectric layer. 15. The method of claim 13 , wherein the positive layer and the negative layer each comprise one of a single-sided metalized film and a double-sided metalized film. 16. The method of claim 13 , wherein the positive terminal and the negative terminal collectively define a busbar of the capacitor. 17. The method of claim 16 , wherein the positive terminal and the negative terminal are positioned vertically and in parallel on a same sidewall of the PDN stacks as the first contact layer and the second contact layer. 18. The method of claim 13 , wherein the positive layer comprises a first protruding portion providing contact to the first contact layer and the negative layer comprises a second protruding portion providing contact to the second contact layer. 19. The vehicle of claim 1 , further comprising a laminated busbar having one or more positive layers alternating with one or more negative layers, wherein each of the one or more positive layers and each of the one or more negative layers of the laminated busbar is coupled to a respective one of the positive terminal or the negative terminal of the capacitor. 20. The capacitor of claim 7 , further comprising a laminated busbar having one or more positive layers alternating with one or more negative layers, wherein each of the one or more positive layers and each of the one or more negative layers of the laminated busbar is coupled to a respective one of the positive terminal or the negative terminal of the capacitor.

Assignees

Inventors

Classifications

  • B60L50/60Primary

    using power supplied by batteries (in combination with fuel cells B60L50/75) · CPC title

  • DC to DC converters · CPC title

  • DC to AC converters · CPC title

  • Terminals · CPC title

  • Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

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What does patent US12400797B2 cover?
Aspects of the disclosure include a symmetric direct current (DC) link capacitor having a low parasitic equivalent series L-inductance (ESL). An exemplary capacitor can include one or more positive-dielectric-negative (PDN) stacks having a positive layer, a negative layer, and a dielectric layer between the positive layer and the negative layer. A first contact layer is electrically coupled to …
Who is the assignee on this patent?
Gm Global Tech Operations Llc
What technology area does this patent fall under?
Primary CPC classification B60L50/60. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Aug 26 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).