Multilayer varistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12400774-B2
Application number	US-202217985076-A
Country	US
Kind code	B2
Filing date	Nov 10, 2022
Priority date	Nov 11, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A multilayer varistor includes a sintered body, an internal electrode disposed in the sintered body, a high-resistance layer covering at least part of the sintered body, and an external electrode covering part of the high-resistance layer, the external electrode being electrically connected to the internal electrode. An arithmetic mean roughness of a surface of the high-resistance layer is greater than or equal to 0.06 μm.

First claim

The invention claimed is:

1. A multilayer varistor comprising:
a sintered body;
an internal electrode in the sintered body;
a high-resistance layer covering at least part of the sintered body; and
an external electrode covering part of the high-resistance layer, the external electrode being electrically connected to the internal electrode, wherein:
an arithmetic mean roughness of a surface of the high-resistance layer is greater than or equal to 0.06 μm, and
a mean thickness of the high-resistance layer is greater than or equal to 0.01 μm and less than or equal to 5 μm.

2. The multilayer varistor of claim 1 , wherein
the high-resistance layer has a plurality of raised portions each having a thickness of greater than 1 μm, and
an average length of major axes of the plurality of raised portions is greater than or equal to 10 μm and less than or equal to 50 μm.

3. The multilayer varistor of claim 2 , wherein
a total area of the plurality of raised portions is greater than or equal to 5% and less than or equal to 30% of a whole area of the surface of the high-resistance layer.

4. The multilayer varistor of claim 1 , wherein
the external electrode includes
a primary electrode covering part of the high-resistance layer and
a plating electrode covering at least part of the primary electrode, and

the primary electrode includes silver as a major component.

5. The multilayer varistor of claim 1 , wherein
the sintered body has
a pair of main surfaces opposite to each other,
a pair of side surfaces opposite to each other, and
a pair of end surfaces opposite to each other,

the internal electrode faces the main surfaces,
the external electrode covers one of the end surfaces, and
the arithmetic mean roughness of the surface of the high-resistance layer is greater on the side surfaces than on the main surfaces.

6. The multilayer varistor of claim 1 , wherein
the high-resistance layer includes SiO 2 as a major component.

7. A multilayer varistor comprising:
a sintered body;
an internal electrode in the sintered body;
a high-resistance layer covering at least part of the sintered body; and
an external electrode covering part of the high-resistance layer, the external electrode being electrically connected to the internal electrode, wherein:
an arithmetic mean roughness of a surface of the high-resistance layer is greater than or equal to 0.06 μm, and is less than or equal to 0.9 μm.

8. The multilayer varistor of claim 7 , wherein
a mean thickness of the high-resistance layer is greater than or equal to 0.01 μm and less than or equal to 5 μm.

9. A multilayer varistor comprising:
a sintered body having a pair of main surfaces opposite to each other, a pair of side surfaces opposite to each other, and a pair of end surfaces opposite to each other;
an internal electrode disposed in the sintered body, the internal electrode facing the main surfaces;
a high-resistance layer covering at least part of the sintered body; and
an external electrode covering part of the high-resistance layer on one of the end surfaces, the external electrode being electrically connected to the internal electrode,
an arithmetic mean roughness of a surface of the high-resistance layer being greater on the side surfaces than on the main surfaces.

10. A method of manufacturing a multilayer varistor, the method comprising:
a first step of preparing a sintered body including ZnO as a major component, an internal electrode being provided in the sintered body;
a second step of forming a high-resistance layer covering at least part of the sintered body;
a third step of applying a primary electrode paste such that the primary electrode paste covers part of the high-resistance layer and is in contact with part of the internal electrode; and
a fourth step of forming a plating electrode covering at least part of a primary electrode formed from the primary electrode paste,
an arithmetic mean roughness of a surface of the high-resistance layer after the second step being greater than or equal to 0.06 μm and less than or equal to 0.9 μm.

11. The method of claim 10 , wherein
the arithmetic mean roughness of the surface of the high-resistance layer after the second step is greater than an arithmetic mean roughness of a surface of the sintered body after the first step.

12. The method of claim 10 , wherein
the second step includes
spraying, while stirring a plurality of the sintered bodies, a solution including a precursor of the high-resistance layer onto the sintered bodies, and
thermally treating each of the sintered bodies provided with the precursor to form the high-resistance layer.

13. The method of claim 12 , wherein
the solution contains polysilazane.

14. The method of claim 10 , wherein
the first step includes
producing ceramic sheets including ZnO as a major component,
applying an internal electrode paste to some of the ceramic sheets,
stacking, on each other, the ceramic sheets provided with the internal electrode paste and the ceramic sheets not provided with internal electrode paste to obtain a laminate,
cutting the laminate to obtain a laminate body having a lamination surface and a cut surface,
baking the laminate body to obtain the sintered body having a lamination surface and a cut surface,

an arithmetic mean roughness of the cut surface of the sintered body is greater than an arithmetic mean roughness of the lamination surface of the sintered body.

15. A method of manufacturing a multilayer varistor, the method comprising:
a first step of preparing a sintered body including ZnO as a major component, an internal electrode being provided in the sintered body;
a second step of forming a high-resistance layer covering at least part of the sintered body;
a third step of applying a primary electrode paste such that the primary electrode paste covers part of the high-resistance layer and is in contact with part of the internal electrode; and
a fourth step of forming a plating electrode covering at least part of a primary electrode formed from the primary electrode paste,
the second step including
spraying, while mixing and stirring a plurality of the sintered bodies, a solution including a precursor of the high-resistance layer toward the sintered bodies, and
thermally treating each of the sintered bodies provided with the precursor to form the high-resistance layer.

16. The method of claim 15 , wherein
the solution contains polysilazane.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• AKIYAMA Yuto

Classifications

• H01C7/105

  Varistor cores (H01C7/12 takes precedence) · CPC title

• H01C17/283

  Precursor compositions therefor, e.g. pastes, inks, glass frits · CPC title

• H01C1/148 Primary

  the terminals embracing or surrounding the resistive element (H01C1/142 takes precedence) · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01C7/1006

  Thick film varistors · CPC title