Computing systems employing measurement of boot components, such as prior to trusted platform module (TPM) availability, for enhanced boot security, and related methods

Patent metadata

Field	Value
Publication number	US-12399998-B2
Application number	US-202217901184-A
Country	US
Kind code	B2
Filing date	Sep 1, 2022
Priority date	Sep 10, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

In exemplary aspects, to extend the measured boot process performed by a trusted platform module (TPM) circuit to earlier, primitive boot components that are processed before the TPM circuit becomes available to perform boot measurements, a secure boot processing system is configured to measure earlier, primitive boot components. The measured primitive boot components are used to update a virtual configuration register (CR) value in a final virtual CR. The TPM circuit uses the final virtual CR value as an initial starting CR value to measure subsequent boot components to provide end-to-end security for boot operations. In this manner, the final virtual CR value protects boot integrity of boot operations of its CPU even if they occur before availability of the TPM circuit.

First claim

What is claimed is:

1. A multiple (multi-) central processing unit (CPU) computing system, comprising:
a trusted platform module (TPM) circuit comprising a TPM configuration register (CR);
a first CPU comprising a first CR, the first CPU configured to, in response to a first reset signal indicating a boot-up state:
access one or more first boot components; and
for each accessed first boot component among the one or more first boot components:
perform a first boot measurement on the accessed first boot component to generate a first CR value; and
update a first existing CR value stored in the first CR based on the generated first CR value; and

a second CPU comprising a second CR register, the second CPU configured to, in response to a second reset signal indicating the boot-up state:
access one or more second boot components; and
for each accessed second boot component among the one or more second boot components:
perform a second boot measurement on the accessed second boot component to generate a second CR value; and
update a second existing CR value stored in the second CR based on the generated second CR value;

the first CPU further configured to:
merge the first existing CR value and the second existing CR value into a merged CR value; and
communicate the merged CR value to the TPM circuit to be used as an initial CR value to measure subsequent boot components;

the TPM circuit configured to:
store the merged CR value as an existing TPM CR value in the TPM CR;
access one or more subsequent boot components; and
for each accessed subsequent boot component among the one or more subsequent boot components:
perform a subsequent boot measurement on the accessed subsequent boot component to generate a subsequent TPM CR value; and
update the existing TPM CR value stored in the TPM CR based on the generated subsequent TPM CR value.

2. The multi-CPU computing system of claim 1 , wherein:
the first CPU comprises one or more first CPU cores, and a first secure boot processing system comprising a first boot processor;
the second CPU comprises one or more second CPU cores, and a second secure boot processing system comprising a second boot processor;
the first boot processor is configured to, in response to the first reset signal indicating the boot-up state:
access the one or more first boot components; and
for each accessed first boot component among the one or more first boot components:
perform the first boot measurement on the accessed first boot component to generate the first CR value; and
update the first existing CR value stored in the first CR based on the generated first CR value; and

the second boot processor is configured to, in response to the second reset signal indicating the boot-up state:
access the one or more second boot components; and
for each accessed second boot component among the one or more second boot components:
perform the second boot measurement on the accessed second boot component to generate the second CR value; and
update the second existing CR value stored in the second CR based on the generated second CR value.

3. The multi-CPU computing system of claim 2 , wherein:
the first CR is inaccessible by the one or more first CPU cores; and
the second CR is inaccessible by the one or more second CPU cores.

4. The multi-CPU computing system of claim 1 , wherein:
the first CPU further comprises a first boot read-only-memory (ROM) storing a first boot ROM program; and
the second CPU further comprises a second boot ROM storing a second boot ROM program;
the first CPU configured to, in response to the first reset signal indicating the boot-up state, execute the first boot ROM program in the first boot ROM to:
access the one or more first boot components; and
for each accessed first boot component among the one or more first boot components:
perform the first boot measurement on the accessed first boot component to generate the first CR value; and
update the first existing CR value stored in the first CR based on the generated first CR value.

5. The multi-CPU computing system of claim 4 , wherein:
the first CPU is further configured to, in response to the first reset signal indicating the boot-up state, execute the first boot ROM program in the first boot ROM to:
load in a first bootloader program from an external memory as a first boot component among the one or more first boot components; and
access the first bootloader program as an accessed first boot component among the one or more first boot components; and

the second CPU is further configured to, in response to the second reset signal indicating the boot-up state, execute the second boot ROM program in the second boot ROM to:
load in a second bootloader program from a second external memory as a second boot component among the one or more second accessed boot components; and
access the second bootloader program as an accessed second boot component among the one or more second accessed boot components.

6. The multi-CPU computing system of claim 4 , wherein:
a first boot component among the one or more first boot components comprises the first boot ROM; and
a second boot component among the one or more second boot components comprises the second boot ROM.

7. The multi-CPU computing system of claim 1 , further comprising:
a board management controller (BMC) configured to generate a power-on-reset (POR) signal in response to a power cycle or reset of the computing system;
the first CPU is configured to receive the first reset signal in response to the BMC generating the POR signal; and
the second CPU is configured to receive the second reset signal in response to the BMC generating the POR signal.

8. The multi-CPU computing system of claim 1 , wherein:
the first CPU is further configured to, in response to the first reset signal indicating the boot-up state, reset the first existing CR value to zero; and
the second CPU is further configured to, in response to the second reset signal indicating the boot-up state, reset the first existing CR value to zero.

9. The multi-CPU computing system of claim 1 , wherein:
the first CR comprises a first platform CR (PCR); and
the second CR comprises a second platform CR (PCR).

10. The multi-CPU computing system of claim 9 , wherein:
the first CPU is configured to:
perform the first boot measurement by being configured to: generate the first CR value of the accessed first boot component based on performing a first digest of the first boot component based on a CR digest; and
update the first existing CR value by being configured to: perform a second digest on the first existing CR value stored in the first PCR, concatenated with the generated first CR value, based on the CR digest; and

the second CPU is configured to:
perform the second boot measurement by being configured to: generate the second CR value of the accessed second boot component based on performing a third digest of the second boot component based on the CR digest; and
update the first existing CR value by being configured to: perform a fourth digest on the second existing CR value stored in the second PCR, concatenated with the generated second CR value, based on the CR digest.

11. The multi-CPU computing system of claim 1 , wherein:
the first CR comprises a first virtual CR; and
the second CR comprises a second virtual CR.

12. The multi-CPU computing system of claim 1 , wherein:
the first CPU is further configured to, in response to the second reset signal indicating the boot-up state, communicate a slave boot-up synchronization signal indicating the boot-up state on a sideband communicati

Assignees

• Ampere Computing Llc

Inventors

• Kumar Vivek
• Abdulhamid Harb Ali
• Ho Loc

Classifications

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F21/575 Primary

  Secure boot · CPC title