Processing device for intermediate value scaling

Patent metadata

Field	Value
Publication number	US-12399717-B2
Application number	US-202318175050-A
Country	US
Kind code	B2
Filing date	Feb 27, 2023
Priority date	Mar 2, 2022
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A processing device comprising: a control register configured to store a scaling factor; at least one execution unit configured to execute instructions to perform arithmetic operations on input floating-point numbers provided according to a first floating-point format, wherein each of the input floating-point numbers provided according to the first floating-point format comprises a predetermined number of bits, wherein the at least one execution unit is configured to, in response to execution of an instance of a first of the instructions: perform processing of a first set of the input floating-point numbers to generate a result value, the result value provided in a further format and comprising more the predetermined number of bits, enabling representation of a greater range of values than is representable in the first floating-point format; and apply the scaling factor specified in the control register to increase or decrease an exponent of the result value.

First claim

The invention claimed is:

1. A system comprising:
at least one execution unit;
a control register configured to store a scaling factor;
a memory configured to store floating-point numbers in a first floating-point format, each of the floating-point numbers in the first floating-point format comprising a first quantity of bits;
one or more additional registers configured to store operands each comprising a set of the floating-point numbers loaded from the memory; and
a hardware module of the at least one execution unit,
wherein the at least one execution unit is configured to:
execute instructions to perform arithmetic operations on the operands, wherein the hardware module comprises arithmetic processing circuitry configured to perform the arithmetic operations,

wherein the hardware module is configured to, in response to execution of an instance of a first instruction of the instructions:
perform processing by the arithmetic processing circuitry of a first of the operands comprising a first set of the floating-point numbers to generate a result value, the result value provided in a further floating-point format and comprising more than the first quantity of bits, wherein the further floating-point format enables representation of a greater range of values than is representable in the first floating-point format; and
apply the scaling factor stored in the control register to increase or decrease an exponent of the result value.

2. The system of claim 1 , wherein the processing of the first set of the floating-point numbers comprises performing at least one multiplication using the first set of the floating-point numbers.

3. The system of claim 1 , wherein the first floating-point format is an 8-bit floating-point format.

4. The system of claim 1 , wherein the at least one execution unit comprises an accumulator configured to store state in accordance with a second floating-point format,
wherein the at least one execution unit is configured to, in response to the execution of the instance of the first of the instructions:
convert the result value to the second floating-point format; and
following the converting the result value to the second floating-point format and the applying the scaling factor specified in the control register to increase or decrease the exponent of the result value, use the result value to update the state stored in the accumulator.

5. The system of claim 4 , wherein the second floating-point format is a single precision format.

6. The system of claim 1 , wherein the at least one execution unit is configured to generate the result value by, in response to the execution of the instance of the first of the instructions:
in addition to processing the first set of the floating-point numbers, performing processing by the arithmetic processing circuitry of a second set of the floating-point numbers.

7. The system of claim 6 , wherein the arithmetic processing circuitry comprises a plurality of multipliers, wherein the at least one execution unit is configured to generate the result value by, in response to the execution of the instance of the first of the instructions:
provide as inputs to each of the multipliers, one respective value of the first set of the floating-point numbers and one respective value of the second set of the floating-point numbers.

8. The system of claim 7 , wherein the arithmetic processing circuitry comprises addition circuitry configured to perform one or more summations of outputs of the multipliers to generate the result value.

9. The system of claim 6 , wherein the second set of the floating-point numbers are provided in a second floating-point format having a first representable range that is less than a second representable range for the further floating-point format in which the result value is provided.

10. The system of claim 1 , wherein the at least one execution unit is configured to, prior to the execution of the instance of the first of the instructions, determine the scaling factor in dependence upon bias values associated with the first set of the floating-point numbers and bias values associated with a second set of the floating-point numbers.

11. The system of claim 1 , wherein the at least one execution unit is configured to:
following the execution of the instance of the first of the instructions, execute an instance of a further instruction to store an updated scaling factor in the control register; and
execute a further instance of the first of the instructions to:
perform processing by the arithmetic processing circuitry with respect to a further set of the floating-point numbers to generate a further result value; and
apply the updated scaling factor specified in the control register to increase or decrease an exponent of the further result value.

12. The system of claim 11 , wherein at least one floating-point number of the further set of the floating-point numbers has an associated bias that is different to a bias associated with at least one floating-point number of the first set of the floating-point numbers.

13. The system of claim 1 , wherein the first set of the floating-point numbers comprises a first set of activation values of a first layer of a neural network,
wherein the processing by the arithmetic processing circuitry to generate the result value comprises performing a dot product between the first set of activation values and a set of weights, wherein the result value represents a contribution of the first set of activation values to an activation value of a second layer of the neural network.

Assignees

• Graphcore Ltd

Inventors

• Alexander Alan
• Knowles Simon
• Felix Stephen
• Luschi Carlo
• Noune Badreddine
• Gore Mrudula
• Da Costa Godfrey
• Andrews Edward
• Masters Dominic

Classifications

• G06F9/30014

  with variable precision · CPC title

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F9/30101 Primary

  Special purpose registers · CPC title