High-speed data transfers through storage device connectors

Patent metadata

Field	Value
Publication number	US-12399657-B2
Application number	US-202217986883-A
Country	US
Kind code	B2
Filing date	Nov 14, 2022
Priority date	Mar 20, 2019
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

Data storage systems, devices and methods may use a switch board configured to communicate using a high-speed multi-level signaling protocol, and a midplane having one or more multi-protocol storage device connectors configured to couple the midplane to one or more storage devices, wherein the midplane may be coupled to the switch board and configured to enable the one or more storage devices to communicate with the switch board through the one or more multi-protocol storage device connectors using the high-speed multi-level signaling protocol. The midplane may be coupled to the switch board through one or more high-speed connectors. One or more re-timers may be coupled between one or more of the high-speed connectors and one or more of the multi-protocol storage device connectors. One or more cables may be used to transfer data to and from the multi-protocol storage device connectors.

First claim

The invention claimed is:

1. An apparatus comprising:
a storage device comprising:
a first connector comprising a first multi-protocol storage device connector, wherein the first multi-protocol storage device connector comprises a first pin configured to transfer data using a first protocol and a second protocol; and
a storage controller configured to control data transfers using the first multi-protocol storage device connector and a multi-level signaling protocol, wherein the multi-level signaling protocol uses multi-level pulse amplitude modulation; and

a circuit board comprising:
a second multi-protocol storage device connector, comprising a second pin configured to engage with the first pin and transfer data using the first protocol and the second protocol; and
a third connector having a configuration based on a performance characteristic comprising a linear transmission characteristic within a predetermined frequency range;

wherein the circuit board is configured to transfer data between the second multi-protocol storage device connector and the third connector.

2. The apparatus of claim 1 , wherein the circuit board is configured to transfer data using the multi-level signaling protocol.

3. The apparatus of claim 1 , wherein the circuit board comprises one or more traces configured to transfer data between the second multi-protocol storage device connector and the third connector.

4. The apparatus of claim 1 , wherein the second multi-protocol storage device connector comprises a U.2 compatible connector.

5. The apparatus of claim 1 , wherein the performance characteristic comprises a matched signal characteristic.

6. The apparatus of claim 1 , wherein the multi-level signaling protocol uses a symbol to transfer a first bit of data and a second bit of data.

7. A system comprising:
a first circuit board configured to communicate using a multi-level signaling protocol; and
a second circuit board having a first multi-protocol storage device connector configured to couple the second circuit board to a storage device, wherein the first multi-protocol storage device connector comprises a first pin configured to transfer data using a first protocol and a second protocol;
wherein the multi-level signaling protocol uses multi-level pulse amplitude modulation;
wherein the second circuit board is configured to enable the storage device to communicate, using the first multi-protocol storage device connector, using the multi-level signaling protocol, with the first circuit board;
wherein the first multi-protocol storage device connector is configured to communicate with the first circuit board using a first cable and a second cable;
wherein the first cable has a first connector located on the second circuit board to communicate with the first multi-protocol storage device connector, and a second connector located on the first circuit board;
wherein the second cable has a third connector located on the second circuit board to communicate with a third multi-protocol storage device connector, and a fourth connector located on the first circuit board; and
wherein the storage device comprises:
a second multi-protocol storage device connector comprising a second pin configured to transfer data using the first protocol and the second protocol; and
a storage controller configured to control data transfers using the second multi-protocol storage device connector and the multi-level signaling protocol.

8. The system of claim 7 , wherein the second circuit board is coupled to the first circuit board using a circuit board connector.

9. The system of claim 7 , wherein the second circuit board comprises one or more traces configured to connect the first connector of the first cable to the first multi-protocol storage device connector.

10. The system of claim 7 , wherein the first connector of the first cable is physically coupled to the first multi-protocol storage device connector.

11. The system of claim 7 , wherein the first multi-protocol storage device connector comprises a U.2 compatible connector.

12. A method comprising:
receiving, at a circuit board, using a multi-level signaling protocol, data; and
sending, from the circuit board, to a storage device, using the multi-level signaling protocol, the data;
wherein the multi-level signaling protocol uses multi-level pulse amplitude modulation;
wherein the receiving is performed using a first connector having a configuration based on a performance characteristic comprising a matched signal characteristic;
wherein the sending is performed using a second connector comprising a first multi-protocol storage device connector comprising a first pin configured to transfer data using a first protocol and a second protocol; and
wherein the storage device comprises:
a third connector comprising a second multi-protocol storage device connector comprising a second pin configured to transfer data using the first protocol and the second protocol; and
a storage controller configured to control data transfers using the second multi-protocol storage device connector and the multi-level signaling protocol.

13. The method of claim 12 , wherein the multi-level signaling protocol uses pulse amplitude modulation.

14. The method of claim 13 , wherein the pulse amplitude modulation comprises pulse amplitude modulation level-4 (PAM4) modulation.

15. The method of claim 12 , wherein the multi-level signaling protocol comprises a network protocol.

16. The method of claim 12 , wherein the receiving is performed using a non-volatile memory express over fabric (NVMe-oF) protocol.

17. The method of claim 12 , wherein the first multi-protocol storage device connector comprises a U.2 compatible connector.

18. The method of claim 12 , wherein the first multi-protocol storage device connector is compliant with a Small Form Factor 8639 (SFF-8639) specification.

19. The method of claim 12 , wherein the performance characteristic comprises a linear transmission characteristic within a predetermined frequency range.

20. The method of claim 12 , wherein the multi-level signaling protocol uses a symbol to transfer a first bit of data and a second bit of data.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Olarig Sompong Paul

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2213/0026

  PCI express · CPC title