Memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-12399625-B2
Application number	US-202318106319-A
Country	US
Kind code	B2
Filing date	Feb 6, 2023
Priority date	Aug 31, 2022
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

The present disclosure relates to a memory device, and a method of operating the memory device that includes a memory block including memory cells. The memory device also includes a voltage generator configured to apply a read voltage and pass voltages to word lines coupled to the memory block. The voltage generator is configured to apply the read voltage to a selected word line among the word lines and apply different pass voltages to unselected word lines symmetrical to each other with respect to the selected word line depending on distances to the selected word line, during a read operation on the memory block.

First claim

What is claimed is:

1. A memory device, comprising:
a memory block including memory cells; and
a voltage generator configured to apply a read voltage and pass voltages to word lines coupled to the memory block,
wherein the voltage generator is configured:
to apply a first pass voltage to first unselected word lines neighboring the selected word line,
to apply a second pass voltage, lower than the first pass voltage, to second unselected word lines neighboring the first unselected word lines; and
to apply a third pass voltage having a level between the first and second pass voltages to third unselected word lines neighboring the second unselected word lines.

2. The memory device according to claim 1 , wherein the first pass voltage is a highest pass voltage among the pass voltages.

3. The memory device according to claim 2 , wherein the second pass voltage is a lowest pass voltage among the pass voltages.

4. The memory device according to claim 1 , wherein the voltage generator is configured to apply a fourth pass voltage that is equal to or higher than the second pass voltage and lower than the third pass voltage to remaining unselected word lines, other than the first, second, and third unselected word lines.

5. A memory device, comprising:
a memory block including memory cells; and
a voltage generator configured to apply a read voltage and pass voltages to word lines coupled to the memory block,
wherein the voltage generator is configured:
to apply a first pass voltage to first unselected word lines neighboring the selected word line,
to apply a second pass voltage, lower than the first pass voltage, to second unselected word lines neighboring the first unselected word lines and to third unselected word lines neighboring the second unselected word lines; and
to apply a third pass voltage having a level between the first and second pass voltages to fourth unselected word lines neighboring the third unselected word lines.

6. The memory device according to claim 1 , wherein the voltage generator is configured to:
apply a first pass voltage among the pass voltages to first unselected word lines adjacent to the selected word line, and
apply, after applying the first pass voltage, remaining pass voltages other than the first pass voltage to remaining unselected word lines other than the first unselected word lines.

7. The memory device according to claim 6 , wherein the first pass voltage has a highest level among the pass voltages.

8. The memory device according to claim 6 , wherein the voltage generator is configured to apply the read voltage to the selected word line while applying the remaining pass voltages to the remaining unselected word lines.

9. The memory device according to claim 6 , wherein the voltage generator is configured to apply the read voltage to the selected word line while applying the first pass voltage to the first unselected word lines.

10. The memory device according to claim 6 , wherein the voltage generator is configured to apply, after applying the remaining pass voltages to the remaining unselected word lines, the read voltage to the selected word line.

11. A method of operating a memory device, comprising:
applying a read voltage to a selected word line;
applying a first pass voltage to first unselected word lines adjacent to the selected word line;
applying a second pass voltage, lower than the first pass voltage, to second unselected word lines adjacent to the first unselected word lines; and
applying a third pass voltage having a level between the first and second pass voltages to third unselected word lines adjacent to the second unselected word lines.

12. The method according to claim 11 , wherein the first pass voltage is set to a highest level among pass voltages.

13. The method according to claim 11 , wherein the second pass voltage is set to a lowest level among pass voltages.

14. The method according to claim 11 , wherein applying the second pass voltage and applying the third pass voltage are performed after applying the first pass voltage.

15. The method according to claim 14 , wherein applying the read voltage is performed while applying the first pass voltage is performed.

16. The method according to claim 14 , wherein applying the read voltage is performed while applying the second pass voltage and applying the third pass voltage are performed.

17. The method according to claim 14 , wherein applying the read voltage is performed after applying the second pass voltage and applying the third pass voltage.

18. The method according to claim 11 , further comprising:
applying a fourth pass voltage to remaining unselected word lines other than the first, second, and third unselected word lines.

19. The method according to claim 18 , wherein the fourth pass voltage is equal to or higher than the second pass voltage and lower than the third pass voltage.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title