Display panel, display device

US12399406B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12399406-B2
Application numberUS-202218026650-A
CountryUS
Kind codeB2
Filing dateJun 30, 2022
Priority dateJun 30, 2022
Publication dateAug 26, 2025
Grant dateAug 26, 2025

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present application provides a display panel, including: a substrate, including a display area and a peripheral area surrounding the display area; a first conductive layer, located on a side of the substrate and including a plurality of data lines located in the display area; and a second conductive layer, located on a side of the first conductive layer facing away from the substrate and including at least one first heating line group, the first heating line group includes at least one first heating line, the first heating line extends from the display area to the peripheral area, and the first heating line extends in a direction same as the data line.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display panel, comprising: a substrate, comprising a display area and a peripheral area surrounding the display area; a first conductive layer, located on a side of the substrate and comprising a plurality of data lines located in the display area; and a second conductive layer, located on a side of the first conductive layer facing away from the substrate and comprising at least one first heating line group, wherein the first heating line group comprises at least one first heating line, the first heating line extends from the display area to the peripheral area, and extends in a direction same as an extending direction of the data line; wherein the peripheral area further comprises a first peripheral sub-area and a second peripheral sub-area located on opposite sides of the display area; wherein the second conductive layer further comprises at least one second heating line group located in the first peripheral sub-area, and the second heating line group comprises at least one second heating line; wherein each of the first heating lines in the same first heating line group respectively intersects and connects with each of the second heating lines in one of the second heating line groups; wherein the second conductive layer further comprises at least two third heating line groups located in the second peripheral sub-area, and each of the third heating line groups comprises at least one third heating line; wherein a number of the third heating line groups is twice a number of the second heating line groups; some first heating lines in the same first heating line group intersect and connect with each of the third heating lines in one of the third heating line groups, other first heating lines in the same first heating line group intersect and connect with each of the third heating lines in another one of the third heating line groups; wherein the display panel further comprises at least two heating bonding terminals located in the second peripheral sub-area, one of the third heating line groups is electrically connected to one of the heating bonding terminals, and another one of the third heating line groups is electrically connected to another one of the heating bonding terminals; wherein the first heating line group, the second heating line group, two of the third heating line groups and two of the heating bonding terminals are configured to form a first closed loop; wherein the display panel further comprises at least one electronic static discharge unit located in the peripheral area, and one of the first closed loops is electrically connected to at least one of the electronic static discharge units. 2. The display panel according to claim 1 , wherein an orthographic projection of the first heating line on the substrate at least partially overlaps with an orthographic projection of the data line on the substrate. 3. The display panel according to claim 2 , further comprising a black matrix layer located on a side of the second conductive layer facing away from the substrate, an orthographic projection of a part of the first heating line, located in the display area, on the substrate is located within an orthographic projection of the black matrix layer on the substrate, and the orthographic projection of the data line on the substrate is located within the orthographic projection of the black matrix layer on the substrate. 4. The display panel according to claim 3 , wherein the orthographic projection of the part of the first heating line, located in the display area, on the substrate is located within the orthographic projection of the data line on the substrate. 5. The display panel according to claim 1 , further comprising a plurality of first fan-out lines and a plurality of second fan-out lines located in the second peripheral sub-area, the first fan-out line being electrically connected to the data line, and the second fan-out line being electrically connected to the third heating line group and the heating bonding terminal respectively; wherein an orthographic projection of the first fan-out line on the substrate at least partially overlaps with an orthographic projection of the second fan-out line on the substrate. 6. The display panel according to claim 5 , wherein the display panel is electrically connected to a flexible circuit board and at least one driver chip; wherein the display panel further comprises a plurality of display bonding terminals located in the second peripheral sub-area, in a plane parallel to the substrate, a minimum distance from each of the display bonding terminal to the display area is greater than a minimum distance from the driver chip to the display area; the data line is electrically connected to the driver chip through the first fan-out line, and the driver chip is electrically connected to the flexible circuit board through the display bonding terminal; wherein the heating bonding terminals are arranged in a same row, and the display bonding terminals are arranged in a same row, and a minimum distance between the heating bonding terminals and the edge of the display panel is equal to a minimum distance between the display bonding terminals and the edge of the display panel. 7. The display panel according to claim 6 , wherein each of the display bonding terminals and each of the heating bonding terminals have a same structure, and are all electrically connected to the same flexible circuit board. 8. The display panel according to claim 7 , wherein the heating bonding terminals comprise a first part and a second part, and all of the display bonding terminals are located in an area between the first part and the second part. 9. The display panel according to claim 7 , wherein the display bonding terminals comprise a first part and a second part, all of the heating bonding terminals are located in an area between the first part and the second part; or some heating bonding terminals are located in the area between the first part and the second part, some other heating bonding terminals are located in an area on a side of the first part facing away from the second part, some other heating bonding terminals are located in an area on a side of the second part facing away from the first part. 10. The display panel according to claim 9 , further comprising a test unit located in the second peripheral sub-area, an orthographic projection of the test unit on the substrate does not overlap with the orthographic projections of the first fan-out line and the second fan-out line on the substrate; wherein the heating bonding terminals located in the area between the first part and the second part comprise a first group and a second group, and the test unit is located in an area between the first group and the second group. 11. The display panel according to claim 10 , further comprising a plurality of dummy heating terminals located in the second peripheral sub-area, the dummy heating terminals are arranged in a same row, and are located on a side of the test unit facing away from the display area; wherein a minimum distance between each of the dummy heating terminals and the edge of the display panel is equal to the minimum distance between each of the heating bonding terminals and the edge of the display panel, and each of the dummy heating terminals is electrically connected to the flexible circuit board. 12. The display panel according to claim 5 , further comprising at least one fourth heating line located in the peripheral area, the fourth heating line is disposed around all of the first heating lines, the second heating lines and the third heating lines; wherein a part of the fourth heating line arra

Assignees

Inventors

Classifications

  • Liquid Crystal display [LCD] · CPC title

  • characterised by the use of flexible or folded printed circuits · CPC title

  • Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

  • Arrangements to prevent high voltage or static electricity failures · CPC title

  • Wiring, e.g. gate line, drain line · CPC title

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Frequently asked questions

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What does patent US12399406B2 cover?
The present application provides a display panel, including: a substrate, including a display area and a peripheral area surrounding the display area; a first conductive layer, located on a side of the substrate and including a plurality of data lines located in the display area; and a second conductive layer, located on a side of the first conductive layer facing away from the substrate and in…
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/136209. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 26 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).