Display device

Patent metadata

Field	Value
Publication number	US-12396337-B2
Application number	US-202217720140-A
Country	US
Kind code	B2
Filing date	Apr 13, 2022
Priority date	Jul 5, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A display device is disclosed that includes a first active layer, a gate pattern, a second active layer, and a lower conductive layer. The first active layer is disposed on a substrate. The gate pattern is disposed on the first active layer. The second active layer is disposed on the gate pattern and includes a body portion electrically connected to the gate pattern. The lower conductive layer is disposed between the substrate and the first active layer and includes a first region. At least a part of the first region overlaps an entirety of the body portion of the second active layer.

First claim

What is claimed is:

1. A display device, comprising:
a first semiconductor active layer disposed on a substrate, the first semiconductor active layer including a source and a drain of a first transistor;
a first conductive layer disposed on the first semiconductor active layer, the first conductive layer including a gate pattern and a write scan line, the gate pattern including a gate of the first transistor;
a second semiconductor active layer disposed on the first conductive layer, the second semiconductor active layer including a source and a drain of a third transistor, a source and a drain of a fourth transistor, and a body portion that connects the drain of the third transistor and the drain of the fourth transistor;
a lower conductive layer disposed between the substrate and the first semiconductor active layer and including a first region, at least a part of the first region overlapping an entirety of the body portion of the second semiconductor active layer; and
a light emitting element disposed on the substrate and electrically connected to the drain of the first transistor,
wherein the gate pattern is electrically connected to the body portion,
wherein the body portion overlaps the write scan line, and
wherein the body portion and the write scan line form a boost capacitor.

2. The display device of claim 1 , wherein a width of the first region of the lower conductive layer in a first direction is greater than a width of the body portion of the second semiconductor active layer in the first direction.

3. The display device of claim 2 , wherein a width of the first region of the lower conductive layer in a second direction intersecting the first direction is greater than a width of the body portion of the second semiconductor active layer in the second direction.

4. The display device of claim 1 , wherein an area of the first region of the lower conductive layer is greater than an area of the body portion of the second semiconductor active layer.

5. The display device of claim 1 ,
wherein the write scan line extends in a first direction, and overlapping a part of the body portion of the second semiconductor active layer.

6. The display device of claim 5 , wherein a width of the first region of the lower conductive layer in a second direction intersecting the first direction is greater than a width of the write scan line in the second direction.

7. The display device of claim 1 , further comprising:
a first scan line disposed on the first conductive layer and extending in a first direction; and
a second scan line disposed on the second semiconductor active layer, and overlapping the first scan line.

8. The display device of claim 7 , wherein the second semiconductor active layer further includes an extension portion extending in a second direction intersecting the first direction from the body portion and positioned between the first scan line and the second scan line, and
wherein a width of the extension portion in the first direction is less than a width of the body portion in the first direction.

9. The display device of claim 7 , further comprising:
a gate connection electrode disposed on the second scan line, and connecting the gate pattern and the body portion of the second semiconductor active layer.

10. The display device of claim 9 , further comprising:
a connection electrode disposed on a same layer as the gate connection electrode, and connecting the first semiconductor active layer and the second semiconductor active layer.

11. The display device of claim 1 , wherein the lower conductive layer is configured to transmit a driving voltage.

12. The display device of claim 1 , wherein the lower conductive layer further includes a second region, at least a part of the second region overlapping an entirety of the gate pattern.

13. The display device of claim 1 , wherein a material of the first semiconductor active layer is different from a material of the second semiconductor active layer.

14. The display device of claim 13 , wherein the first semiconductor active layer includes at least one of amorphous silicon and polysilicon, and
wherein the second semiconductor active layer includes an oxide semiconductor.

15. A display device, comprising:
a first pixel disposed on a substrate;
a second pixel disposed on the substrate, and adjacent to the first pixel in a first direction; and
a lower conductive layer disposed between the substrate and the first pixel, and between the substrate and the second pixel,
wherein each of the first pixel and the second pixel includes:
a first semiconductor active layer disposed on the lower conductive layer, the first semiconductor active layer including a source and a drain of a first transistor;
a first conductive layer disposed on the first semiconductor active layer, the first conductive layer including a gate pattern and a write scan line, the gate pattern including a gate of the first transistor;
a second semiconductor active layer disposed on the first conductive layer, the second semiconductor active layer including a source and a drain of a third transistor, a source and a drain of a fourth transistor, and a body portion that connects the drain of the third transistor and the drain of the fourth transistor; and
a light emitting element disposed on the substrate and electrically connected to the first semiconductor active layer,

wherein the lower conductive layer includes a first region, at least a part of the first region overlapping an entirety of the body portion of the second semiconductor active layer of the first pixel and an entirety of the body portion of the second semiconductor active layer of the second pixel,
wherein the gate pattern is electrically connected to the body portion,
wherein the body portion of each of the first pixel and the second pixel overlaps the write scan line, and
wherein the body portion of each of the first pixel and the second pixel, and the write scan line form a boost capacitor of each of the first pixel and the second pixel.

16. The display device of claim 15 , wherein a width of the first region of the lower conductive layer in the first direction is greater than a sum of a width of the body portion of the second semiconductor active layer of the first pixel in the first direction, a width of the body portion of the second semiconductor active layer of the second pixel in the first direction, and a gap between the body portion of the second semiconductor active layer of the first pixel and the body portion of the second semiconductor active layer of the second pixel in the first direction.

17. The display device of claim 16 , wherein a width of the first region of the lower conductive layer in a second direction intersecting the first direction is greater than a width of the body portion of the second semiconductor active layer of the first pixel in the second direction and a width of the body portion of the second semiconductor active layer of the second pixel in the second direction.

18. The display device of claim 15 , wherein an area of the first region of the lower conductive layer is greater than a sum of an area of the body portion of the second semiconductor active layer of the first pixel and an area of the body portion of the second semiconductor active layer of the second pixel.

19. The display device of claim 15 , wherein the first pixel and the second pixel are symmetrical with respect to a second direction intersecting the first direction.

20. The display device of claim 15 , wh

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Junwon

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/121 Primary

  characterised by the geometry or disposition of pixel elements · CPC title