Memory device

Patent metadata

Field	Value
Publication number	US-12394465-B2
Application number	US-202318456430-A
Country	US
Kind code	B2
Filing date	Aug 25, 2023
Priority date	Sep 9, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

According to one embodiment, a memory device includes a pillar extending in a first direction through a first, second, and third conductive layers. The pillar includes ferroelectric layer. A first transistor is at an intersection of the pillar and the first conductive layer. A second transistor is at an intersection of the pillar and the second conductive layer. A ferroelectric memory cell is at an intersection with the third conductive layer and the pillar. A circuit supplies a read pulse to the memory cell in a read sequence. The read pulse has a first voltage value in a first period and has a second voltage value with the same polarity as the first voltage value in a second period after the first period. The second voltage value is lower than the first.

First claim

What is claimed is:

1. A memory device, comprising:
a first conductive layer above a substrate in a first direction;
a second conductive layer between the first conductive layer and the substrate;
a third conductive layer between the first conductive layer and the second conductive layer;
a pillar extending in the first direction and including a ferroelectric layer, the pillar being adjacent to the first, second, and third conductive layers in a second direction perpendicular to the first direction;
a first transistor at an intersection of the first conductive layer and the pillar;
a second transistor at an intersection of the second conductive layer and the pillar;
a memory cell at an intersection of the third conductive layer and the pillar, the memory cell comprising a ferroelectric transistor; and
a circuit configured to supply a read pulse to the memory cell in a read sequence, wherein
the read pulse has:
a first voltage value in a first period, and
a second voltage value in a second period after the first period, the second voltage value having the same polarity as the first voltage value but an absolute magnitude smaller than an absolute magnitude of the first voltage value.

2. The memory device according to claim 1 , wherein the read pulse is applied between a gate and a channel of the ferroelectric transistor.

3. The memory device according to claim 1 , wherein the read pulse has a positive polarity.

4. The memory device according to claim 3 , wherein
the circuit is further configured to supply a write pulse having a third voltage value with a positive polarity to the memory cell in a write sequence, and
the absolute magnitude of the first voltage value is smaller than an absolute magnitude of the third voltage value.

5. The memory device according to claim 3 , wherein the circuit is configured to apply:
a first positive voltage to the first conductive layer, and
a second positive voltage to the pillar, the second positive voltage being smaller than the first positive voltage.

6. The memory device according to claim 1 , wherein the read pulse has a negative polarity.

7. The memory device according to claim 6 , wherein
the circuit is further configured to supply an erase pulse having a fourth voltage value with a negative polarity to the memory cell in an erase sequence, and
the absolute magnitude of the first voltage value is smaller than an absolute magnitude of the fourth voltage value.

8. The memory device according to claim 6 , wherein the circuit is configured to apply:
a third positive voltage to the first conductive layer, and
a fourth positive voltage to the pillar, the fourth positive voltage being larger than the third positive voltage.

9. The memory device according to claim 1 , wherein
the circuit is further configured to supply:
an erase pulse with a first polarity to the memory cell in an erase sequence, and
a first pulse with the first polarity to the memory cell in the read sequence after application of the read pulse with a second polarity different from the first polarity, and

an absolute magnitude of the first pulse is smaller than an absolute magnitude of the erase pulse.

10. The memory device according to claim 1 , wherein
the read pulse has the first voltage value in the read sequence before a first write cycle, and
a second read pulse has a fifth voltage value in a read sequence after the first write cycle, the fifth voltage value having an absolute magnitude larger than the absolute magnitude of the first voltage value.

11. A memory device, comprising:
a first conductive layer above a substrate in a first direction;
a second conductive layer between the first conductive layer and the substrate;
a third conductive layer between the first conductive layer and the second conductive layer;
a pillar extending in the first direction and including hafnium oxide, the pillar being adjacent to the first, second, and third conductive layers in a second direction perpendicular to the first direction;
a first transistor at an intersection of the first conductive layer and the pillar;
a second transistor at an intersection of the second conductive layer and the pillar;
a memory cell at an intersection of the third conductive layer and the pillar, the memory cell comprising a ferroelectric transistor; and
a circuit configured to supply a read pulse to the memory cell in a read sequence, wherein
the read pulse has:
a first voltage value in a first period, and
a second voltage value in a second period after the first period, the second voltage value having the same polarity as the first voltage value but an absolute magnitude smaller than an absolute magnitude of the first voltage value.

12. The memory device according to claim 11 , wherein the read pulse has a positive polarity.

13. The memory device according to claim 12 , wherein
the circuit is further configured to supply a write pulse having a third voltage value with a positive polarity to the memory cell in a write sequence, and
the absolute magnitude of the first voltage value is smaller than an absolute magnitude of the third voltage value.

14. The memory device according to claim 12 , wherein the circuit is configured to apply:
a first positive voltage to the first conductive layer, and
a second positive voltage to the pillar, the second positive voltage being smaller than the first positive voltage.

15. The memory device according to claim 11 , wherein the read pulse has a negative polarity.

16. The memory device according to claim 15 , wherein
the circuit is further configured to supply an erase pulse having a fourth voltage value with a negative polarity to the memory cell in an erase sequence, and
the absolute magnitude of the first voltage value is smaller than an absolute magnitude of the fourth voltage value.

17. The memory device according to claim 15 , wherein the circuit is configured to apply:
a third positive voltage to the first conductive layer, and
a fourth positive voltage to the pillar, the fourth positive voltage being larger than the third positive voltage.

18. The memory device according to claim 15 , wherein the hafnium oxide contains zirconium.

19. The memory device according to claim 11 , wherein
the circuit is further configured to supply:
an erase pulse with a first polarity to the memory cell in an erase sequence, and
a first pulse with the first polarity to the memory cell in the read sequence after application of the read pulse with a second polarity different from the first polarity, and

an absolute magnitude of the first pulse is smaller than an absolute magnitude of the erase pulse.

20. The memory device according to claim 11 , wherein
the read pulse has the first voltage value in the read sequence before a first write cycle, and a second read pulse has a fifth voltage value in a read sequence after the first write cycle, and
an absolute magnitude of the fifth voltage value is larger than the absolute magnitude of the first voltage value.

Assignees

• Kioxia Corp

Inventors

• Tanaka Reika
• Ota Kensuke
• Suzuki Masamichi

Classifications

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2297

  Power supply circuits · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/22

  using ferroelectric elements · CPC title