Display substrate with metal layers and display device

Patent metadata

Field	Value
Publication number	US-12394381-B2
Application number	US-202218044967-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A display substrate includes a driving module arranged on the base substrate, the driving module includes a plurality of driving units, and the driving unit includes a plurality of stages of driving circuits; the driving unit includes a first signal line, and the driving circuit includes an output sub-circuit; the display substrate includes at least two metal layers stacked along a direction away from the base substrate; in at least one driving unit, an orthographic projection of the first signal line on the base substrate at least partially overlaps an orthographic projection of a first electrode or a second electrode of at least one transistor included in the output sub-circuit on the base substrate, the first electrode and the second electrode are arranged on the same metal layer, and the first electrode and the first signal line are arranged on different metal layers.

First claim

What is claimed is:

1. A display substrate, comprising a driving module arranged on a base substrate, wherein the driving module includes a plurality of driving units, and the driving unit includes a plurality of stages of driving circuit; the driving circuit is used to provide a driving signal;
the driving unit includes a first signal line, and the driving circuit includes an output sub-circuit configured to output the driving signal;
the display substrate includes at least two metal layers stacked along a direction away from the base substrate;
in at least one driving unit, an orthographic projection of the first signal line on the base substrate at least partially overlaps an orthographic projection of a first electrode of at least one transistor included in the output sub-circuit on the base substrate, the orthographic projection of the first signal line on the base substrate at least partially overlaps an orthographic projection of a second electrode of the at least one transistor included in the output sub-circuit on the base substrate;
the first electrode and the second electrode are arranged on a same metal layer, and the first electrode and the first signal line are arranged on different metal layers;
wherein the driving module includes a first driving unit; the first driving unit includes a plurality of stages of first driving circuits, and the first driving circuit is used to provide a first driving signal; the first driving unit includes a first first voltage line and a first second voltage line; the first driving circuit includes a first output sub-circuit; the first signal line is the first first voltage line;
the first output sub-circuit includes a first driving transistor and a first driving reset transistor;
a first electrode of the first driving transistor is electrically connected to the first second voltage line, a second electrode of the first driving transistor is electrically connected to a first electrode of the first driving reset transistor, and a second electrode of the first driving reset transistor is electrically connected to the first first voltage line;
the display substrate includes a first metal layer and a second metal layer sequentially stacked along a direction away from the base substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor and the second electrode of the first driving reset transistor are both arranged on the first metal layer, and the first first voltage line is arranged on the second metal layer;
an orthographic projection of the first electrode of the first driving transistor on the base substrate at least partially overlaps the orthographic projection of the first first voltage line on the base substrate; an orthographic projection of the second electrode of the first driving transistor on the base substrate at least partially overlaps the orthographic projection of the first first voltage line on the base substrate; an orthographic projection of the first electrode of the first driving reset transistor on the base substrate at least partially overlaps the orthographic projection of the first first voltage line on the base substrate; an orthographic projection of the second electrode of the first driving reset transistor on the base substrate at least partially overlaps the orthographic projection of the first first voltage line on the base substrate.

2. The display substrate according to claim 1 , wherein an orthographic projection of a first signal line included in one driving circuit of the plurality of driving units on the base substrate at least partially overlaps an orthographic projection of a second signal line included in another driving unit of the plurality of driving units on the base substrate.

3. The display substrate according to claim 2 , wherein the first signal line and the second signal line are configured to provide a same signal.

4. The display substrate according to claim 2 , wherein the first signal line is a low voltage DC signal line, a high voltage DC signal line or a clock signal line;
the second signal line is a low voltage DC signal line, a high voltage DC signal line or a clock signal line.

5. The display substrate according to claim 1 , wherein among the plurality of driving units, orthographic projections of at least three signal lines on the base substrate at least partially overlap.

6. The display substrate according to claim 1 , wherein the driving module includes a first driving unit; the first driving unit includes a plurality of stages of first driving circuits, and the first driving circuit is used to provide a first driving signal; the first driving unit includes a first first voltage line and a first second voltage line; the first driving circuit includes a first output sub-circuit; the first signal line is the first first voltage line;
the first output sub-circuit includes a first driving transistor and a first driving reset transistor;
a first electrode of the first driving transistor is electrically connected to the first second voltage line, a second electrode of the first driving transistor is electrically connected to a first electrode of the first driving reset transistor, and a second electrode of the first driving reset transistor is electrically connected to the first first voltage line;
the display substrate includes a first metal layer, a second metal layer and a third metal layer which are sequentially stacked along a direction away from the base substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all arranged on the first metal layer, and the first first voltage line is arranged on the third metal layer;
an orthographic projection of the first electrode of the first driving transistor on the base substrate at least partially overlaps the orthographic projection of the first first voltage line on the base substrate; an orthographic projection of the second electrode of the first driving transistor on the base substrate at least partially overlaps the orthographic projection of the first first voltage line on the base substrate; an orthographic projection of the first electrode of the first driving reset transistor on the base substrate at least partially overlaps the orthographic projection of the first first voltage line on the base substrate; an orthographic projection of the second electrode of the first driving reset transistor on the base substrate at least partially overlaps with the orthographic projection of the first first voltage line on the base substrate.

7. The display substrate according to claim 1 , wherein the first driving unit further includes a second first voltage line, a first first clock signal line, a first second clock signal line, a first second voltage line, a first start signal line and a first reset line;
the first first clock signal line, the first second clock signal line and the first reset line are all arranged on the first metal layer;
the second first voltage line, the first start signal line and the first second voltage line are all arranged on the second metal layer.

8. The display substrate according to claim 7 , wherein the first driving circuit includes a first on-off control transistor and a second on-off control transistor;
both a gate electrode of the first on-off control transistor and a gate electrode of the second on-off transistor are electrically connected to the second first voltage line;
at least part of an orthographic projection of the second first voltage line on the base substrate is arran

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shan Zhenzhen
• Lu Jiangnan
• Shang Guangliang
• Liu Libin
• Zhu Jianchao
• Yao Xing

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G3/3258 Primary

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title