Display device, display system and distributed function system

US12394380B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12394380-B2
Application numberUS-202117623679-A
CountryUS
Kind codeB2
Filing dateDec 24, 2021
Priority dateDec 2, 2021
Publication dateAug 19, 2025
Grant dateAug 19, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The embodiment of the present application discloses a display device, a display system and a distributed function system. The initial pixel driving data corresponding to the image to be displayed, which is received, is segmented into a plurality of pixel driving data blocks by the management chip. With the display screen comprising a plurality of display modules, and the pixel driving data blocks are written to the driving circuits of the corresponding display modules through the data connection lines based on control signals. The driving circuit is employed to drive pixels in the display module to work according to the pixel driving data block, which is received to meet the display requirements of full HD and resolutions above full HD.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device, comprising a management chip and a display screen and a display panel, the management chip and the display screen are disposed on the display panel, wherein the management chip is connected to the display screen through data connection lines, and the display screen comprises a plurality of display circuits and a plurality of first function circuits, and each of the display circuits comprises a plurality of display units, and each of the first function circuits comprises a plurality of first function units, and the plurality of first function units are arranged between adjacent display units, and each of the display circuits is provided with a driving circuit; wherein the management chip is employed to determine initial pixel driving data of an image to be displayed according to the image to be displayed, which is received, and pack the initial pixel driving data into a plurality of pixel driving data blocks according to parameters of the display circuits, and write the pixel driving data blocks to the driving circuits of the corresponding display circuits through the data connection lines based on control signals; the driving circuit of the display circuits is employed to drive pixels in the display circuits to work according to the pixel driving data block, which is received, wherein a peak value of a processing capability of the driving circuit is greater than or equal to processing parameters required for processing the pixel driving data block; wherein the management chip comprises a function processing circuit, and the function processing circuit is configured to: obtain a resolution of the display screen and arrangement parameters of the display circuits before the management chip is employed to determine initial pixel driving data of an image to be displayed according to the image to be displayed, which is received, wherein the resolution of the display screen is determined by resolutions of the display circuits and the arrangement parameters of the display circuits; and under a condition that a resolution of the image to be displayed is higher than the resolution of the display screen, down-sample the image to be displayed so that a resolution of the image to be displayed, which is processed, is same as the resolution of the display screen, or under a condition that a resolution of the image to be displayed is lower than the resolution of the display screen, add redundant pixel rows and/or add redundant pixel columns to the image to be displayed, so that a resolution of the image to be displayed, which is processed, is same as the resolution of the display screen. 2. The display device according to claim 1 , wherein a number of pixel driving data blocks is the same as a number of display circuits. 3. The display device according to claim 1 , wherein the plurality of display circuits are arranged in an N*M array, and a number of the data connection lines is m correspondingly, and each data connection line is respectively connected to the N display circuits in a corresponding column, where m=M, and M is a positive integer greater than 1 , and N is a positive integer greater than 1. 4. The display device according to claim 1 , wherein the plurality of display circuits are arranged in an N*M array, and a number of the data connection lines is n correspondingly, and each data connection line is respectively connected to the M display circuits in a corresponding row, where n=N, and M is a positive integer greater than 1, and N is a positive integer greater than 1. 5. The display device according to claim 1 , wherein the plurality of display circuits are arranged in an N*M array, and a number of the data connection lines is n*m correspondingly, and each data connection line is respectively connected to the corresponding display circuits, where m=M, n=N, and M is a positive integer greater than 1, and N is a positive integer greater than 1. 6. The display device according to claim 1 , wherein the management chip is employed to sequentially write each pixel driving data block to the driving circuit of the corresponding display circuit through the data connection line according to a fixed period. 7. The display device according to claim 6 , wherein the management chip further comprises a storage module, and the storage module is employed for storing the pixel driving data blocks corresponding to the respective display circuits when the display circuits display the image to be displayed. 8. The display device according to claim 1 , wherein the management chip is employed to write the corresponding pixel driving data blocks to the driving circuits of the corresponding display circuits through the data connection lines when the management chip determines that the respective display circuits start to work. 9. The display device according to claim 1 , wherein the control signals are transmitted to a first row of display circuits in a first direction in the display screen through a control connection line, and the first row of display circuits transmits the control signals to other display circuits in a second direction. 10. The display device according to claim 1 , wherein the control signals are transmitted to the display screen through the control connection lines, and a number of the control connection lines is the same as a number of the display circuits, and respective control connection lines are connected to the respective display circuits, and the management chip transmits the control signals to the respective display circuits through the corresponding control connection lines. 11. The display device according to claim 1 , wherein the display screen comprises a first frequency display area and a second frequency display area, and the management chip is employed to control the display circuits in the first frequency display area to refresh display at a first frequency, and control the display circuits in the second frequency display area to refresh display at a first frequency at a second frequency. 12. The display device according to claim 11 , wherein the first frequency display area is arranged around the second frequency display area. 13. The display device according to claim 1 , wherein display frequencies of the respective display circuits to refresh display are different. 14. The display device according to claim 1 , wherein the management chip is employed to segment the image to be displayed according to arrangement parameters of the display circuits to obtain sub-images to be displayed corresponding to the respective display circuits, and determine sub-initial pixel driving data corresponding to the respective display circuits according to the sub-images to be displayed, and pack the sub-initial pixel driving data into the corresponding pixel driving data blocks. 15. The display device according to claim 1 , wherein the management chip is employed to process the image to be displayed according to the resolution of the display screen, the resolutions of the display circuits, and the arrangement parameters of the display circuits, so that the resolution of the image to be displayed matches the resolution of the display screen. 16. The display device according to claim 1 , wherein the data connection line comprises a data connection line pair or a single data connection line. 17. The display device according to claim 1 , wherein the display device comprises a plurality of management chips, and each of the plurality of management chips processes a part of the image to be displayed, and parts of the image to be displayed processed by the respective

Assignees

Inventors

Classifications

  • Control of matrices with row and column drivers · CPC title

  • Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions · CPC title

  • Solving problems of bandwidth in display systems · CPC title

  • Parallel handling of streams of display data · CPC title

  • Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

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What does patent US12394380B2 cover?
The embodiment of the present application discloses a display device, a display system and a distributed function system. The initial pixel driving data corresponding to the image to be displayed, which is received, is segmented into a plurality of pixel driving data blocks by the management chip. With the display screen comprising a plurality of display modules, and the pixel driving data bloc…
Who is the assignee on this patent?
Wuhan China Star Optoelectronics Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3258. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 19 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).