Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12394374-B2
Application number	US-202218029356-A
Country	US
Kind code	B2
Filing date	Jun 21, 2022
Priority date	Jun 21, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A display substrate and a display device are provided, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes a pixel circuit, a scan drive circuit, a control drive circuit and a buffer drive circuit; the pixel circuit includes a node reset transistor, a writing transistor, a reset signal line connected to a control electrode of the node reset transistor, a scan signal line connected to a control electrode of the writing transistor, and a control signal line; reset signal lines of pixel circuits of first to K-th rows are electrically connected with the buffer drive circuit, reset signal lines of pixel circuits of (K+1)-th to N-th row are electrically connected with the scan drive circuit or the control drive circuit.

First claim

The invention claimed is:

1. A display substrate, comprising a base substrate and a circuit structure layer disposed on the base substrate, wherein the circuit structure layer comprises a plurality of pixel circuits, a scan drive circuit, a control drive circuit and a buffer drive circuit; each pixel circuit of the plurality of pixel circuits comprises a node reset transistor, a writing transistor, a reset signal line, a scan signal line, and a control signal line, the reset signal line is connected with a control electrode of the node reset transistor, the scan signal line is connected with a control electrode of the writing transistor;
reset signal lines of pixel circuits of first row to K-th row of the plurality of pixel circuits are electrically connected with the buffer drive circuit, reset signal lines of pixel circuits of (K+1)-th row to N-th row of the plurality of pixel circuits are electrically connected with the scan drive circuit or the control drive circuit, such that a difference between a start time of signals of scan signal lines or control signal lines of the plurality of pixel circuits being an effective signal and an end time of signals of reset signal lines of the plurality of pixel circuits being an effective level signal is greater than or equal to a threshold time, and N is a total number of rows of the plurality of pixel circuits.

2. The display substrate according to claim 1 , wherein each pixel circuit of the plurality of pixel circuits further comprises a drive transistor, the threshold time t is approximately equal to K*(1/f)/N, or K*(1/f)/(N+N0), or Tstress, where f is a refresh frequency of the display substrate, N0 is a sum of number of blank rows executed by the display substrate before and/or after operation of the N rows pixel circuit, N0 is a positive integer greater than or equal to 0, and Tstress is a recovery time of a threshold voltage of a biased drive transistor.

3. The display substrate according to claim 1 , wherein scan signal lines of the pixel circuits of the first row to the N-th row of the plurality of pixel circuits are electrically connected to the scan drive circuit, and control signal lines of the pixel circuits of the first row to the N-th row of the plurality of pixel circuits are electrically connected to the control drive circuit;
when a transistor type of the node reset transistor is the same as a transistor type of the writing transistor, the reset signal lines of the pixel circuits of the (K+1)-th row to the N-th row of the plurality of pixel circuits are electrically connected with the scan drive circuit; each pixel circuit of the plurality of pixel circuits further comprises a compensation transistor and a compensation reset transistor; a transistor type of the compensation reset transistor is opposite to transistor types of the drive transistor, the node reset transistor, the writing transistor and the compensation transistor; the scan signal line is further electrically connected with a control electrode of the compensation transistor, and a control signal line is electrically connected with a control electrode of the compensation reset transistor;
when the transistor type of the node reset transistor is opposite to that the transistor type of the writing transistor, the reset signal lines of the pixel circuits of the (K+1)-th row to the N-th of the plurality of pixel circuits are electrically connected with the control drive circuit, and each pixel circuit of the plurality of pixel circuits further comprises the compensation transistor; the transistor types of the node reset transistor and the compensation transistor are opposite to the transistor types of the drive transistor and the writing transistor; the control signal line is electrically connected with the control electrode of the compensation transistor.

4. The display substrate according to claim 1 , comprising a display area and a non-display area, wherein the non-display area comprises a bezel area surrounding a periphery of the display area and a bonding area located at a side of the bezel area away from the display area;
the scan drive circuit, the control drive circuit and the buffer drive circuit are located in the display area and/or the non-display area;
when the scan drive circuit, the control drive circuit and the buffer drive circuit are located in the non-display area, the scan drive circuit and the control drive circuit are located at a first side and a second side of the display area which are opposite to each other, the buffer drive circuit is located at a third side of the display area away from the bonding area, or a fourth side of the display area close to the bonding area.

5. The display substrate according to claim 4 , further comprising a light emitting drive circuit, wherein each pixel circuit of the plurality of pixel circuits further comprises a light emitting transistor and a light emitting signal line; the light emitting signal line is electrically connected with a control electrode of the light emitting transistor;
the light emitting drive circuit is located at a side of the control drive circuit away from the display area;
light emitting signal lines of pixel circuits of the first row to the N-th row of the plurality of pixel circuits are electrically connected with the light emitting drive circuit;
for pixel circuits in a same row of the plurality of pixel circuits, a difference between a start time of signals of light emitting signal lines of the row of pixel circuits being an effective level signal and an end time of signals of reset signal lines of the row of pixel circuits being an effective level signal is greater than a sum of the threshold time and a duration of signals of scan signal lines of the row of pixel circuits being an effective level signal.

6. The display substrate according to claim 1 , further comprising a test circuit and a multiplexing circuit; each pixel circuit of the plurality of pixel circuits further comprises a data signal line extending in a second direction, a first direction intersects with the second direction, the first direction is an extension direction of the reset signal line, the scan signal line and the control signal line;
the data signal line is electrically connected with a first electrode of the writing transistor, the test circuit and the multiplexing circuit respectively; and
the test circuit is located at a first side and a third side of a display area, and the multiplexing circuit is located at the first side and/or a second side of the display area.

7. The display substrate according to claim 6 , wherein when the reset signal lines of the pixel circuits of the (K+1)-th row to the N-th row of the plurality of pixel circuits are electrically connected to the scan drive circuit, the buffer drive circuit comprises K cascaded buffer shift registers; the scan drive circuit comprises N cascaded scan shift registers; the control drive circuit comprises N/2 cascaded control shift registers, an output terminal of a buffer shift register of last stage is electrically connected with an input terminal of a scan shift register of first stage;
a buffer shift register of a-th stage is electrically connected with a reset signal line of a pixel circuit of a-th row, 1≤a≤K;
a scan shift register of b-th stage is electrically connected with a scan signal line of a pixel circuit of b-th row, 1≤b≤N;
a scan shift register of c-th stage is electrically connected with a reset signal line of a pixel circuit of (K+c)-th row, 1≤c≤N−K;
a control shift register of d-th stage is electrically connected to control signal lines of pixel circuits of (2d−1)-th row and 2d-th row respectively, 1≤d≤N/2.

8. The display substrate according to claim 7 , wherein scan shift registers of first stage to (N−

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Liu Song
• Zhou Yang
• Bai Lu
• Dai Junxiu
• Li Lingtong
• Wei Liheng
• Chen Tianci

Classifications

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title