Display panel and display device

US12394369B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12394369-B2
Application numberUS-202418733532-A
CountryUS
Kind codeB2
Filing dateJun 4, 2024
Priority dateMay 6, 2021
Publication dateAug 19, 2025
Grant dateAug 19, 2025

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first direction and the second direction intersect; the at least one driver circuit includes a plurality of shift register circuits disposed in cascade and a shift register circuit of the plurality of shift register circuits is located between adjacent light-emitting element rows of the plurality of light-emitting element rows.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising a display area; wherein the display panel further comprises: a light-emitting element, wherein the light-emitting element is located in the display area; a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element; a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and pixel circuit rows, wherein at least one of the pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the pixel circuit rows are arranged along a second direction, the first direction and the second direction intersect; wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded and at least one stage of shift register circuit is located between adjacent pixel circuit rows; and at least one stage of shift register circuit comprises at least two shift register circuit modules and adjacent shift register circuit modules are connected through at least one trace; wherein at least one of the following is satisfied: a shift register circuit module and a gap between adjacent pixel circuits overlap along the second direction; or, at least one of the pixel circuit rows comprises a plurality of pixel circuit groups, a pixel circuit group of the plurality of pixel circuit groups comprises at least two pixel circuits, and a shift register circuit module and a gap between adjacent pixel circuit groups overlap along the second direction. 2. The display panel of claim 1 , wherein at least one of the following is satisfied: at least two shift register circuit modules are arranged along the first direction; or, at least one trace connected between adjacent shift register circuit modules extends along the first direction. 3. The display panel of claim 1 , wherein at least one of the following is satisfied: different shift register circuit modules and gaps between different adjacent pixel circuits respectively overlap along the second direction; or, different shift register circuit modules and gaps between different adjacent pixel circuit groups respectively overlap along the second direction. 4. The display panel of claim 1 , wherein at least one of the following is satisfied: the shift register circuit modules in a shift register circuit and at least two different gaps between adjacent pixel circuits overlap along the second direction; or the shift register circuit modules in a shift register circuit and at least two different gaps between adjacent pixel circuit groups overlap along the second direction. 5. A display panel, comprising a display area; wherein the display panel further comprises: a light-emitting element, wherein the light-emitting element is located in the display area; a pixel circuit, wherein the pixel circuit is located in the display area and the pixel circuit is configured to drive the light-emitting element; a driver circuit, wherein the driver circuit is located in the display area and the driver circuit is configured to provide a drive signal to the pixel circuit; and pixel circuit rows, wherein at least one of the pixel circuit rows comprises a plurality of pixel circuits arranged along a first direction, the pixel circuit rows are arranged along a second direction, the first direction and the second direction intersect; wherein the driver circuit comprises a plurality of stages of shift register circuits cascaded and at least one stage of shift register circuit is located between adjacent pixel circuit rows; and at least one stage of shift register circuit comprises at least two shift register circuit modules and adjacent shift register circuit modules are connected through at least one trace; wherein at least one of the following is satisfied: the pixel circuit and at least one trace connected between adjacent shift register circuit modules overlap along the second direction; or the pixel circuit row comprises a plurality of pixel circuit groups, a pixel circuit group of the plurality of pixel circuit groups comprises at least two pixel circuits, the pixel circuit group and at least one trace connected between adjacent shift register circuit modules overlap along the second direction. 6. The display panel of claim 1 , wherein the driver circuit comprises a scan driver circuit and the scan driver circuit provides a scan signal for the pixel circuit; and the scan driver circuit comprises a plurality of stages of scan shift register circuits cascaded and at least one stage of scan shift register circuit is located between adjacent pixel circuit rows; the scan shift register circuit comprises a first latch module, a logic module and a first buffer module, and the first latch module, the logic module and the first buffer module are arranged along the first direction. 7. The display panel of claim 1 , wherein the driver circuit comprises a light-emitting control driver circuit, and the light-emitting control driver circuit provides a light-emitting control signal for the pixel circuit; the light-emitting control driver circuit comprises a plurality of stages of light-emitting control shift register circuits cascaded, and at least one stage of light-emitting control shift register circuit is located between adjacent pixel circuit rows; and the light-emitting control shift register circuit comprises a second latch module and a second buffer module, the second latch module and the second buffer module are arranged along the first direction. 8. The display panel of claim 1 , further comprising a plurality of data lines extending along the second direction; wherein a data line of the plurality of data lines comprises a winding part, and the winding part does not overlap with the shift register circuit module along a direction perpendicular to a base substrate of the display panel. 9. The display panel of claim 1 , wherein the pixel circuit row comprises a plurality of pixel circuit groups, and a pixel circuit group of the plurality of pixel circuit groups comprises at least two pixel circuits; along the first direction, a width of one stage of shift register circuit is greater than a width of at least one pixel circuit group. 10. The display panel of claim 1 , wherein at least one of the following is satisfied: lengths of at least two shift register circuit modules along the first direction are not equal; or widths of at least two shift register circuit modules along the second direction are not equal. 11. The display panel of claim 1 , further comprising: a plurality of driver circuits arranged along the first direction; wherein at least two shift register circuits of at least two driver circuits of the plurality of driver circuits each comprises at least two shift register circuit modules. 12. The display panel of claim 11 , wherein along the first direction, at least two shift register circuit modules in the at least two shift register circuits are arranged in a reverse order. 13. The display panel of claim 11 , wherein the at least two shift register circuit modules comprise a buffer module and a latch module; along the first direction, an arrangement order of the buffer module and the latch module in one shift register circuit is reverse to an arrangement order of the buffer module and latch module in another shift register circuit. 14. The display panel of claim 11 , wherein the at least two shift register circuit modules comprise a buffer module and a latch module; along the first directi

Assignees

Inventors

Classifications

  • Arrangements to prevent high voltage or static electricity failures · CPC title

  • Layout of electrodes and connections · CPC title

  • Integration of the drivers onto the display substrate · CPC title

  • Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

  • Details of a shift registers arranged for use in a driving circuit · CPC title

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Frequently asked questions

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What does patent US12394369B2 cover?
Disclosed are a display panel and a display device. The display panel includes a display area, a plurality of light-emitting elements located in the display area, and at least one driver circuit located in the display area; the plurality of light-emitting elements includes a plurality of light-emitting element rows extend in a first direction and arranged in a second direction, where the first …
Who is the assignee on this patent?
Hubei Yangtze Ind Innovation Center Of Advanced Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 19 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).