Communication with serial periphal interface information

Patent metadata

Field	Value
Publication number	US-12393546-B2
Application number	US-202218547646-A
Country	US
Kind code	B2
Filing date	Apr 6, 2022
Priority date	Apr 7, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

Communication devices, systems and methods are disclosed. In one example, a communication device includes: a communication unit that adds identification information for identifying a data block to a set of data blocks having a serial signal group conforming to SPI transmitted from a master in synchronization with a clock, and transmits the data block to a communication partner device within one frame period of a predetermined communication protocol, or adds identification information for identifying each of the data blocks, and transmits the data block to the communication partner device in a plurality of frame periods; and a storage unit that sequentially stores a number of data blocks transmitted from the master, and then outputs a data block transmitted from the communication partner device in response to the number of data blocks, to transmit the data block to the master.

First claim

The invention claimed is:

1. A communication device comprising:
communication circuitry that includes identification information in a packet that includes data blocks having a serial signal group conforming to a serial peripheral interface (SPI), the data blocks transmitted from a master in synchronization with a reference clock, the identification information identifying the data blocks, and that transmits the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or that transmits the data blocks to the communication partner device in a plurality of frame periods; and
a memory that sequentially stores a predetermined number of the data blocks transmitted from the master, and then outputs an other data block transmitted from a slave via the communication partner device in response to storing the predetermined number of the data blocks from the master, to transmit the other data block to the master, wherein
the communication circuitry further includes a transmission mode information and an SPI mode information in the packet,
the transmission mode information indicates whether all of a plurality of frames corresponding to the data blocks are to be transmitted in a time division duplex (TDD) burst or fewer than all of the plurality of frames corresponding to the data blocks are to be transmitted in the TDD burst, and
the SPI mode information indicates a transmission processing type that is based upon a clock polarity setting and a clock phase setting corresponding to the reference clock.

2. A communication device comprising:
communication circuitry that includes identification information in a packet that includes data blocks having a serial signal group conforming to a serial peripheral interface (SPI), the data blocks transmitted from a master in synchronization with a reference clock, the identification information identifying the data blocks, and that transmits the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or that transmits the data blocks to the communication partner device in a plurality of frame periods;
a memory that sequentially stores a predetermined number of the data blocks transmitted from the master, and then outputs an other data block transmitted from a slave via the communication partner device in response to storing the predetermined number of the data blocks from the master, to transmit the other data block to the master;
a first counter that measures a length of a frame period on a basis of the reference clock; and
a second counter that counts the number of the data blocks transmitted from the master,
wherein the memory sequentially stores the predetermined number of the data blocks at timing corresponding to count values of the first counter and the second counter, and then outputs the other data block.

3. The communication device according to claim 2 ,
wherein the reference clock is a clock of a frequency defined by an Automotive SerDes Alliance (ASA) standard, and
the second counter performs a counting operation in synchronization with a clock included in a serial signal group conforming to the SPI.

4. A communication device comprising:
communication circuitry that includes identification information in a packet that includes data blocks having a serial signal group conforming to a serial peripheral interface (SPI), the data blocks transmitted from a master in synchronization with a reference clock, the identification information identifying the data blocks, and that transmits the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or that transmits the data blocks to the communication partner device in a plurality of frame periods; and
a memory that sequentially stores a predetermined number of the data blocks transmitted from the master, and then outputs an other data block transmitted from a slave via the communication partner device in response to storing the predetermined number of the data blocks from the master, to transmit the other data block to the master, wherein
a first period that is a period in which the predetermined number of the data blocks transmitted from the master are stored in the memory is equal to or longer than a second period that is a period in which the communication circuitry transmits a packet including the other data block to the communication partner device.

5. The communication device according to claim 4 , wherein the second period is longer than a half period of the first period.

6. The communication device according to claim 4 , wherein the communication circuitry transmits the other data block stored in the memory to the communication partner device in the frame period after the second period elapses from when the predetermined number of the data blocks transmitted from the master are stored in the memory.

7. The communication device according to claim 4 , wherein the communication circuitry transmits the other data block stored in the memory to the communication partner device in the frame period before the second period elapses from when the predetermined number of the data blocks transmitted from the master are stored in the memory.

8. The communication device according to claim 7 , wherein, in a case where a given data block to be transmitted to the communication partner device is not ready, the communication circuitry stops transmitting the given data block to the communication partner device until a next frame period.

9. The communication device according to claim 8 , wherein, in a case where the given data block from the communication partner device does not arrive, the memory is delayed from storing the given data block until a next frame period.

10. The communication device according to claim 4 , further comprising a shift register that sequentially stores the predetermined number of the data blocks transmitted from the master in the memory every first period, and then sequentially reads the data blocks transmitted from the communication partner device and stored in the memory every first period from the memory and transmits the data blocks to the master.

11. The communication device according to claim 10 , wherein the shift register sequentially reads data blocks from the communication partner device stored in the memory and transmits the data blocks to the master, without transmitting an interrupt signal indicating that a data block from the communication partner device has arrived to the master.

12. The communication device according to claim 1 , wherein the communication circuitry transmits a data block from the master to the communication partner device and receives a data block from the communication partner device in different periods within a given frame period using a communication protocol according to TDD with the communication partner device.

13. A non-transitory computer readable medium storing a program for controlling a communication device, the program being executable by a processor to perform operations comprising:
including identification information in a packet that includes data blocks having a serial signal group conforming to a serial peripheral interface (SPI), the data blocks transmitted from a master in synchronization with a reference clock, the identification information identifying the data blocks;
transmitting the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or transmitting the data blocks to the communication partner device in a plurality of frame periods;
sequentially storing a predetermined number of

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Hyakudai Toshihisa
• Yamada Junya
• Ota Satoshi

Classifications

• G06F13/4291

  using a clocked protocol · CPC title

• G06F13/362

  with centralised access control · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title