Methods and apparatus to align media workloads

Patent metadata

Field	Value
Publication number	US-12393471-B2
Application number	US-202117359308-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to align processing events. An example apparatus includes a comparator to compare a value of a counter to a threshold value, the threshold value associated with an amount of time to defer provision of a first or second input signal to a corresponding first or second IP device, respectively, signal deferring circuitry to defer provision of the first or second input signals to a corresponding one of the first or second IP devices based on an output of the comparator, deferral of the first or second input signals to cause alignment of first and second processing events performed by the first and second IP devices, respectively, and power controlling circuitry to cause the first and second IP devices to power down based on completion of the first and second processing events.

First claim

What is claimed is:

1. An apparatus comprising:
a comparator to compare a counter value to a threshold value, the threshold value associated with an amount of time to defer provision of at least one of a first input signal to a first device or a second input signal to a second device;
signal deferring circuitry to defer provision of the at least one of the first input signal or the second input signal based on comparison of the counter value to the threshold value, deferral of the at least one of the first input signal or the second input signal to cause alignment of a first processing event performed by the first device and a second processing event performed by the second device;
a watch dog timer to determine whether an expected time of arrival of the first input signal exceeds an expiration time of the watch dog timer;
signal supplying circuitry to cause transmission of the second input signal to an output port based on the expected time of arrival of the first input signal exceeding the expiration time of the watch dog timer; and
power controlling circuitry to cause the first device and the second device to power down based on completion of the first processing event and the second processing event.

2. The apparatus of claim 1 , wherein the threshold value is based on a difference between a selected start time and a time at which the second input signal is to be supplied to the second device.

3. The apparatus of claim 1 , wherein the second input signal is to be provided as a second output signal to a second output port at a same time as the first input signal is to be supplied to a first output port, the first output port is coupled to the first device, the second output port is coupled to the second device, and the second output signal is to be used by the second device to perform the second processing event.

4. The apparatus of claim 1 , wherein the first device and the second device are implemented as part of a video conferencing application.

5. The apparatus of claim 1 , wherein addition of (i) a first amount of time extending from a selected start time to a completion time at which both the first processing event and the second processing event have completed and (ii) a second amount of time during which the first device and the second IP device are powered down corresponds to (iii) a third amount of time to process a portion of a data frame, the data frame including at least one of: 1) audio data, 2) video data, or 3) audio data and video data.

6. The apparatus of claim 5 , wherein including:
threshold value determining circuitry to increase the threshold value by a length of time corresponding to a portion of a total amount of time to process the data frame; and
wherein the signal deferring circuitry is to control, based on the increased threshold value, deferral of another first input signal received after the first device and the second device have exited a power down state, the power down state corresponding to a state in which the first device and the second device are powered down.

7. The apparatus of claim 1 , including:
a process length comparator to compare a first duration of time corresponding to the first processing event, a second duration of time corresponding to the second processing event, and a third duration of time corresponding to a third processing event to identify a longest duration of time among the first duration of time, the second duration of time, and the third duration of time; and
threshold value determining circuitry to determine a first threshold value and a second threshold value to cause all of the first processing event, the second processing event, and the third processing event to be started and completed within the longest duration of time.

8. The apparatus of claim 1 , wherein the deferral of the at least one of the first input signal or the second input signal is to cause the first processing event and the second processing event to be aligned to at least one of start or complete at a same time.

9. An apparatus comprising:
at least one memory;
instructions; and
at least one processor circuit to be programmed based on the instructions to:
compare a first duration of time corresponding to a first processing event, a second duration of time corresponding to a second processing event, and a third duration of time corresponding to a third processing event to identify a longest duration of time among the first duration of time, the second duration of time, and the third duration of time, the first processing event performed by a first device, the second processing event performed by a second device and the third processing event performed by a third device;
determine a first threshold value and a second threshold value to cause the first processing event, the second processing event, and the third processing event to be started and completed within the longest duration of time;
cause provision of at least one of a first input signal to the first device, a second input signal to the second IP devices device or a third input signal to the third device to be deferred based on the first threshold value and the second threshold value; and
cause the first device and the second device to power down based on completion of the first processing event and the second processing event.

10. The apparatus of claim 9 , wherein one or more of the at least one processor circuit is to determine the first threshold value based on a difference between a selected start time and a time at which the second input signal is to be supplied to the second device.

11. The apparatus of claim 9 , wherein one or more of the at least one processor circuit is to:
determine whether an expected time of arrival of the first input signal exceeds an expiration time; and
cause transmission of the second input signal to an output port based on the expected time of arrival of the first input signal exceeding the expiration time.

12. The apparatus of claim 9 , wherein the first device and the second device are implemented as part of a video conferencing application.

13. The apparatus of claim 9 , wherein addition of (i) a first amount of time extending from a selected start time to a completion time at which both the first processing event and the second processing event have completed and (ii) a second amount of time during which the first device and the second IP device are powered down corresponds to (iii) a third amount of time to process a portion of a data frame, the data frame including at least one of: 1) audio data, 2) video data, or 3) audio data and video data.

14. The apparatus of claim 13 , wherein one or more of the at least one processor circuit is to:
increase the first threshold value by a length of time corresponding to a portion of a total amount of time to process the data frame; and
control, based on the increased first threshold value, deferral of another first input signal received after the first device and the second device have exited a power down state, the power down state corresponding to a state in which the first device and the second device are powered down.

15. The apparatus of claim 9 , wherein one or more of the at least one processor circuit is to defer provision of the least one of the first input signal, the second input signal or the third input signal to cause at least the first processing event and the second processing event to be aligned to at least one of start or complete at a same time.

16. At least one non-transitory computer readable medium comprising instructions to cause at least one processor circuit to at least:
compare a count

Assignees

• Intel Corp

Inventors

• Srivastava Charu
• Wang Changliang
• Potluri Srikanth
• Gerber Nir
• Bian Qixiong
• Baran Stanley

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F9/542 Primary

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F1/3228 Primary

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title