Panel impedance sensing via driver replica current

Patent metadata

Field	Value
Publication number	US-12392811-B2
Application number	US-202318122061-A
Country	US
Kind code	B2
Filing date	Mar 15, 2023
Priority date	Mar 15, 2023
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A circuit includes a driver to provide a voltage at a node of a load and a first circuit to facilitate determining a load current at the node. The load is a capacitive load and the first circuit facilitates determining the load current by measuring a replica current and determining a capacitance of the load using values of the voltage and the replica current.

First claim

What is claimed is:

1. An apparatus, comprising:
a driver circuit configured to provide a voltage at a node of a load, the voltage based on a first current;
a first circuit configured to generate a second current proportional to the first current; and
a second circuit configured to measure the first current by:

measuring the second current; and
determining a capacitance of the load using values of the voltage and the second current; and
a current measurement circuit configured to provide a measurable voltage proportional to the second current, determine a resistance-capacitance (RC) model parameter associated with the load via measurements at different frequencies used to determine the capacitance.

2. The apparatus of claim 1 , wherein:
the load comprises at least a portion of a touch-display panel, and
the first current comprises a pixel current provided to the touch-display panel.

3. The apparatus of claim 1 , wherein the voltage comprises a voltage having a sinusoidal waveform.

4. The apparatus of claim 1 , wherein the voltage comprises a peak-to-peak voltage.

5. The apparatus of claim 1 , wherein:
the second current comprises a first peak-to-peak value, and
the first current comprises a load current comprising a second peak-to-peak value equal to the first peak-to-peak value.

6. The apparatus of claim 1 , wherein the first circuit comprises a bias-current source configured to provide a component to the second current.

7. The apparatus of claim 1 , further comprising a current measurement circuit configured to provide a measurable voltage proportional to the second current.

8. The apparatus of claim 1 , wherein the current measurement circuit comprises a trans-impedance amplifier circuit configured to provide the measurable voltage.

9. The apparatus of claim 1 , further comprising circuitry configured to remove an effect of a parasitic capacitance of the first circuit.

10. A circuit for impedance sensing, the circuit comprising:
a driver circuit configured to provide a voltage at a node, the voltage being based on a first circuit configured to generate a current, and
a second circuit coupled to the node, the second circuit configured to:

measure the current;
determining an admittance at the node by using the current and the voltage; and
a current measurement circuit configured to provide a measurable voltage proportional to the second current, determine a resistance-capacitance (RC) model parameter associated with the load via measurements at different frequencies used to determine the capacitance.

11. The circuit of claim 10 , wherein the admittance comprises a capacitive admittance, and the node is part of a touch-display panel.

12. The circuit of claim 10 , wherein the second circuit is configured to determine the admittance by using peak-to-peak values of the current and the voltage.

13. The circuit of claim 10 , wherein the second circuit comprises a bias-current source configured to provide a component to the third current.

14. The circuit of claim 13 , further comprising a trans-impedance amplifier circuit configured to provide a measurable voltage proportional to the current.

15. The circuit of claim 14 , wherein:
the voltage comprises a stimulus voltage configured to electrically stimulate a third circuit coupled to the driver circuit at the node and operating at a frequency, and
the admittance is based on the frequency.

16. The circuit of claim 10 , further comprising circuitry configured to remove a parasitic capacitance of the first circuit.

17. An apparatus, comprising:
a display panel;
a first circuit configured to provide a voltage at a node of the display panel, wherein the voltage is based on a first current; and
a second circuit coupled to the node and configured to:
receive a second current proportional to the first current;
determine a value of the second current;
determine a capacitance of the display panel by using peak-to-peak values of the voltage and the second current; and
a current measurement circuit configured to provide a measurable voltage proportional to the second current, determine a resistance-capacitance (RC) model parameter associated with the load via measurements at different frequencies used to determine the capacitance.

18. The apparatus of claim 17 , further comprising a current-measurement circuit, wherein:
the second circuit comprises a bias-current source configured to provide a component to the second current to the current-measurement circuit,
the current-measurement circuit is configured to determine the value of the second current by providing a measurable voltage proportional to the second current.

19. The apparatus of claim 18 , wherein the current-measurement circuit comprises a trans-impedance amplifier circuit configured to provide the measurable voltage.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Kwan Tom W
• Hu Yue
• Su Feng
• Wei Guowen
• Lin Fang
• Mehr Iuri

Classifications

• G06F3/044

  by capacitive means · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G01R19/0046

  characterised by a specific application or detail not covered by any other subgroup of G01R19/00 · CPC title

• G01R27/02 Primary

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title